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HC05H12GRS/D Rev. 1.0
68HC(7)05H12
General Release Specification Rev. 1.0
November, 1998 NON-DISCLOSURE
AGREEMENT
REQUIRED
General Release Specification REQUIRED AGREEMENT
NON-DISCLOSURE
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
(c) Motorola, Inc., 1997 General Release Specification 2 MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
List of Sections
List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU and Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16-Bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . 115 Serial Communications Interface (SCI). . . . . . . . . . . . 125 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 143 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA List of Sections
General Release Specification 1
NON-DISCLOSURE
AGREEMENT
REQUIRED
List of Sections REQUIRED Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . 159 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 173 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . 183 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
NON-DISCLOSURE
General Release Specification 2 List of Sections
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 1.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Section 2. Memory
2.1 2.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 2.5
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Table of Contents
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General Release Specification 3
NON-DISCLOSURE
1.6 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.3 OSC1, OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.5 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.6 PA0-PA7/Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . 22 1.6.7 PB0-PB7/ECLK, MISO, MOSI, SCK. . . . . . . . . . . . . . . . . . 22 1.6.8 PC0-PC7/TCAP0-3, TCMP0-1, RDI, TDO . . . . . . . . . . . . 22 1.6.9 PD0-PD3/AN0-AN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.10 VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.11 PE0-PE7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.12 PF0-PF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.13 PVDD1, PVSS1, PVDD2, PVSS2 . . . . . . . . . . . . . . . . . . . . 23
AGREEMENT
REQUIRED
Table of Contents REQUIRED
2.6 2.7 2.8 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 User EPROM (for the 705 version only) . . . . . . . . . . . . . . . . . . 35 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. CPU and Instruction Set
3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AGREEMENT
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 3.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
NON-DISCLOSURE
3.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . 46 3.7.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 47 3.7.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Section 4. Interrupts
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
General Release Specification 4 Table of Contents
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Table of Contents
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 External Interrupt (IRQ/Keyboard) . . . . . . . . . . . . . . . . . . . . . . 63 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16-Bit Timer1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16-Bit Timer2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Section 5. Resets
5.1 5.2 5.3 5.4 5.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . . 70 5.6.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 COP During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . 71 5.6.4 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.7 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 Low Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8.1 LVR Operation in WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Table of Contents
General Release Specification 5
NON-DISCLOSURE
AGREEMENT
REQUIRED
Table of Contents REQUIRED Section 6. Operating Modes
6.2 6.3 6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.2 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.3 Slow Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AGREEMENT
Section 7. Input/Output Ports
7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.1 Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2 Port A Interrupt Edge Register . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 Port A Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . 81 7.3.4 Port A Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . 82 7.4 7.5 7.6 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
NON-DISCLOSURE
7.7 Port E and Port F (Power Drivers) . . . . . . . . . . . . . . . . . . . . . . 83 7.7.1 Power Drivers for 360Air Core Driven Instruments. . . . . . 85 7.7.2 H-Bridge Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7.3 Power Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.4 Short Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.5 Port E and Port F Mismatch Registers . . . . . . . . . . . . . . . . 89 7.7.6 Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.7.7 Port E and Port F Configurations . . . . . . . . . . . . . . . . . . . . 92 7.7.8 H-Bridge Control with the PWM . . . . . . . . . . . . . . . . . . . . . 94 7.8 7.9 8.1 Port E and Port F During WAIT Mode . . . . . . . . . . . . . . . . . . . 95 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
General Release Specification 6 Table of Contents
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Table of Contents
Section 8. Core Timer
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 Core Timer Status and Control Register (CTSCR) . . . . . . . 99 8.3.2 Computer Operating Properly (COP) Watchdog Reset. . . 101 8.3.3 Core Timer Counter Register (CTCR). . . . . . . . . . . . . . . . 101 8.4 Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.1 9.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4
Timer During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Section 10. Serial Peripheral Interface (SPI)
10.1 10.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10.3 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . 117 10.3.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4 SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.5.1 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . 121
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Table of Contents General Release Specification 7
NON-DISCLOSURE
9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.2 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.3 Output Compare Register 1 . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.4 Output Compare Register 2 . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.6 Input Capture Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.7 Input Capture Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.8 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.9 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.10 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
AGREEMENT
Section 9. 16-Bit Timers
REQUIRED
Table of Contents REQUIRED
10.5.2 10.5.3 10.6 SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . 123 SPI Data I/O Register (SPDAT) . . . . . . . . . . . . . . . . . . . . 124 SPI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Section 11. Serial Communications Interface (SCI)
11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
AGREEMENT
11.4 Receiver Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4.1 Idle Line Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.2 Address Mark Wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.5 11.6 11.7 Receive Data (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Transmit Data (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
NON-DISCLOSURE
11.8 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8.1 Serial Communications Data Register (SCDAT). . . . . . . . 135 11.8.2 Serial Communications Control Register 1 (SCCR1) . . . . 136 11.8.3 Serial Communications Control Register 2 (SCCR2) . . . . 137 11.8.4 Serial Communications Status Register (SCSR) . . . . . . . 138 11.8.5 Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . 140 11.9 SCI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Section 12. Analog to Digital Converter
12.1 12.2 12.3 12.4 12.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Internal and Master Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 145
12.6 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6.1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 146 12.6.2 A/D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7 12.8
General Release Specification 8 Table of Contents
A/D During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Table of Contents
12.9 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 150 12.9.1 Transfer Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.2 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.3 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.4 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.5 Gain Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.6 Differential Linearity Error . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.7 Integral Linearity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.8 Total Unadjusted Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Section 13. EEPROM
13.1 13.2 13.3 13.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . . . 154 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . . . 155
13.5 EEPROM Read, Erase and Programming Procedures . . . . . 156 13.5.1 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.2 Erase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.3 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.6 Operation in WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Section 14. Pulse Width Modulator (PWM)
14.1 14.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3.1 PWM Channel Microshifting . . . . . . . . . . . . . . . . . . . . . . . 161 14.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.4.1 PWM Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.4.2 PWM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4.3 PWM Channel Enable Register. . . . . . . . . . . . . . . . . . . . . 165 14.4.4 PWM Channel Polarity Register . . . . . . . . . . . . . . . . . . . . 165 14.5 PWM During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Table of Contents
General Release Specification 9
NON-DISCLOSURE
AGREEMENT
REQUIRED
Table of Contents REQUIRED Section 15. EPROM
15.1 15.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.3 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.4.1 EPROM Programming Register (EPROG) . . . . . . . . . . . . 170 15.5 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . 171
AGREEMENT
Section 16. Electrical Characteristics
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 176 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 178 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
NON-DISCLOSURE
16.10 Power Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.11 Power-on Reset/Low Voltage Reset Characteristics . . . . . . . 181
Section 17. Mechanical Specifications
17.1 17.2 17.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Index
General Release Specification 10 Table of Contents
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
List of Figures
Figure 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 4-1 5-1 5-2 5-3 5-4 6-1 7-1 7-2 7-3 7-4 7-5 Title Page MC68HC(7)05H12 Block Diagram . . . . . . . . . . . . . . . . . . . . 19 MC68HC(7)05H12 Pin Assignments (52-pin PLCC package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MC68HC(7)05H12 Memory Map . . . . . . . . . . . . . . . . . . . . . 26 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Registers $0000-$000F . . . . . . . . . . . . . . . . . . . . . . . . . 29 I/O Registers $0010-$001F . . . . . . . . . . . . . . . . . . . . . . . . . 30 I/O Registers $0020-$002F . . . . . . . . . . . . . . . . . . . . . . . . . 31 I/O Registers $0030-$003F . . . . . . . . . . . . . . . . . . . . . . . . . 32 I/O Registers $0040-$004F . . . . . . . . . . . . . . . . . . . . . . . . . 33 System Control Register (SYSCR). . . . . . . . . . . . . . . . . . . . 34 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . . 62 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . 69 COP Watchdog Timer Location Register (COPR) . . . . . . . . 72 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 WAIT Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port A Interrupt Edge Register (PAIED) . . . . . . . . . . . . . . . . 81 Port A Interrupt Control Register (PAICR) . . . . . . . . . . . . . . 81 Port A Interrupt Status Register (PAISR) . . . . . . . . . . . . . . . 82 Port E and Port F (Power Drivers) . . . . . . . . . . . . . . . . . . . . 84 Driving Cross Coupled Coils . . . . . . . . . . . . . . . . . . . . . . . . 85
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA List of Figures
General Release Specification 11
NON-DISCLOSURE
AGREEMENT
REQUIRED
List of Figures REQUIRED
7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 H-Bridge Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Power Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Short Circuit Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . 88 Port E Mismatch Register (PEMISM) . . . . . . . . . . . . . . . . . . 89 Port F Mismatch Register (PFMISM) . . . . . . . . . . . . . . . . . . 90 H-Bridge States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Port E Configuration for two 360 instruments . . . . . . . . . . . 92 Port F Configuration for four 90 instruments (version 1). . . 93 Port F Configuration for four 90 instruments (version 2). . . 93 H-Bridge Control with PWM . . . . . . . . . . . . . . . . . . . . . . . . . 94 Correspondence between Data and PWM Values. . . . . . . . 95 Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Core Timer Status and Control Register (CTSCR) . . . . . . . 99 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . 102 Timer Block Diagram (Timer1) . . . . . . . . . . . . . . . . . . . . . . 104 16-Bit Timer Register Addresses (Timer1). . . . . . . . . . . . . 105 Timer Control Register 1 (TCR1) . . . . . . . . . . . . . . . . . . . . 110 Timer Control Register 2 (TCR2) . . . . . . . . . . . . . . . . . . . . 112 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . 113 Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 118 Serial Peripheral Block Diagram . . . . . . . . . . . . . . . . . . . . 119 Serial Peripheral Interface Master-Slave Interconnection . 120 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 121 SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . 123 SPI Data I/O Register (SPDAT) . . . . . . . . . . . . . . . . . . . . . 124 Serial Communications Interface Block Diagram . . . . . . . . 128 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Sampling Technique Used On All Bits . . . . . . . . . . . . . . . . 132 Examples of Start Bit Sampling Techniques . . . . . . . . . . . 133 SCI Artificial Start Following a Framing Error. . . . . . . . . . . 134 SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . 134 SCI Data Register (SCDAT). . . . . . . . . . . . . . . . . . . . . . . . 135 SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . 136 SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . 137
NON-DISCLOSURE
AGREEMENT
General Release Specification 12 List of Figures
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
List of Figures
14-5 14-6 15-1 15-2 15-3 17-1 17-2
PWM Channel Enable Register (PWMEN) . . . . . . . . . . . . 165 PWM Channel Polarity Register (PWMPOL) . . . . . . . . . . . 165 MC68HC705H12 Programming Circuit . . . . . . . . . . . . . . . 169 EPROM Programming Register (EPROG). . . . . . . . . . . . . 170 Mask Options Registers (MOR1 and MOR2) . . . . . . . . . . . 171 52-Pin PLCC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . 183 52-Pin PLCC Package Dimensions . . . . . . . . . . . . . . . . . . 184
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA List of Figures
General Release Specification 13
NON-DISCLOSURE
AGREEMENT
11-10 11-11 12-1 12-2 12-3 12-4 13-1 13-2 14-1 14-2 14-3 14-4
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . 138 SCI Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . 140 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 146 A/D Data Register (ADDR). . . . . . . . . . . . . . . . . . . . . . . . . 148 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . 149 Transfer Curve of an Ideal 8-Bit A/D Converter . . . . . . . . . 150 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . 154 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . 155 PWM Block Diagram (one channel) . . . . . . . . . . . . . . . . . . 160 PWM Microshifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 PWM Data Registers (PWM0-7) . . . . . . . . . . . . . . . . . . . . 163 PWM Control Register (PWMCTL). . . . . . . . . . . . . . . . . . . 164
REQUIRED
List of Figures REQUIRED NON-DISCLOSURE
General Release Specification 14 List of Figures
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
List of Tables
Table 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 6-1 7-1 8-1 8-2 10-1 11-1 11-2 12-1 12-2 13-1 14-1 15-1 Title Page Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 46 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 47 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 50 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 61 Operating Mode Entry Conditions . . . . . . . . . . . . . . . . . . . . . 75 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Minimum COP Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . 101 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 First Prescaler Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Second Prescaler Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 A/D Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 A/D Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PWM Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA List of Tables
General Release Specification 15
NON-DISCLOSURE
AGREEMENT
REQUIRED
List of Tables REQUIRED NON-DISCLOSURE
General Release Specification 16 List of Tables
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2 Introduction
The MC68HC(7)05H12 HCMOS microcomputer is a member of the M68HC05 family. This 8 bit microcomputer unit (MCU) contains on-chip oscillator, CPU, RAM, (EP)ROM, monitor ROM, EEPROM, parallel I/O, one core timer, COP watchdog system, two 16-bit programmable timers, synchronous and asynchronous serial interface, a 4 channel A/D converter, and an 8 channel 8-bit PWM with on-chip power driver circuitry.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA General Description General Release Specification 17
NON-DISCLOSURE
1.6 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.3 OSC1, OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.5 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.6 PA0-PA7/Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . 22 1.6.7 PB0-PB7/ECLK, MISO, MOSI, SCK. . . . . . . . . . . . . . . . . . 22 1.6.8 PC0-PC7/TCAP0-3, TCMP0-1, RDI, TDO . . . . . . . . . . . . 22 1.6.9 PD0-PD3/AN0-AN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.10 VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.11 PE0-PE7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.12 PF0-PF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.13 PVDD1, PVSS1, PVDD2, PVSS2 . . . . . . . . . . . . . . . . . . . . 23
AGREEMENT
REQUIRED
General Description REQUIRED 1.3 Features
* * * * * HC05 core 52 PLCC package 12032 bytes of user (EP)ROM + 240 bytes of monitor ROM + 16 bytes user vectors 256 bytes of RAM 256 bytes of EEPROM Multipurpose core timer, real time interrupt (RTI), COP watchdog timer Two 16-bit timers with two input captures and two output compares each Serial peripheral interface (SPI) Serial communications interface (SCI) 4 channel A/D converter (8-bit resolution) Keyboard interrupt for 8 I/O lines 8 channel 8-bit PWM system for control of H-bridge drivers 12 special power drivers to drive two major gauges and four minor gauges, with short circuit detection and slew rate limitation for reduced RFI (EMC) Power saving WAIT mode 2 selectable bus frequencies (slow mode) Low voltage reset (LVR) circuitry to hold the CPU in reset
AGREEMENT
* * * * * * * *
NON-DISCLOSURE
* * *
General Release Specification 18 General Description
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Description Features
User (EP)ROM -- 12032 Bytes User Vectors --16 Bytes
PA7 PA6 PORT A PA5 PA4 PA3 PA2 PA1 PA0 PB7/ SCK
Monitor ROM -- 240 Bytes
User RAM -- 256 Bytes
DDR A
User EEPROM -- 256 Bytes
CPU Control
Data Direction Register B
Arithmetic/Logic Unit Accumulator
PB6/ MOSI PB5/ MISO PORT B PB4 PB3 PB2/ECLK PB1 PB0
IRQ
M68HC05 MCU Index Register RESET Stack Pointer 00000000111 Program Counter
RESET
Data Direction Register C
00 Condition Code Register 111HI NCZ CPU CLOCK OSC1 OSC2 Internal Oscillator Divide by 2 or 8 Core Timer, COP
PC7/ TDO PC6/ RDI PC5/TCMP1 PORT C PC4/TCMP0 PC3/TCAP3
PC1/TCAP1 PC0/TCAP0 PORT D
16-Bit Timer1
16-Bit Timer2 package: 52PLCC PWM System SCI
PD3-0/ AN3-0
PE7-0
SPI VSS VDD AVDD VREFH 8-Bit A/D Converter
PF3-0
Power
2 x PVDD 2 x PVSS
Figure 1-1. MC68HC(7)05H12 Block Diagram
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA General Description
General Release Specification 19
NON-DISCLOSURE
PC2/TCAP2
PORT F PORT E
AGREEMENT
REQUIRED
Key Interrupt Mask Register
General Description REQUIRED 1.4 Mask Options
There are three mask options: * * * COP watchdog timer (enable/disable) Low voltage reset (LVR) (enable/disable) Ports E/F in WAIT mode (enable/disable)
AGREEMENT
1.5 Pin Assignments
Figure 1-2 shows the PLCC pin assignments.
PB6/MOSI
PB5/MISO
PB7/SCK
PD3/AN3
PD2/AN2
PD1/AN1
PD0/AN0
IRQ/VPP
RESET
OSC1
OSC2
VSS
7 VREFH AVDD VDD PC0/TCAP0 PC1/TCAP1 8 1
PB4 47 46 PB3 PB2/ECLK PB1 PB0 PA7 PA6
NON-DISCLOSURE
PC2/TCAP2 PC3/TCAP3 PC4/TCMP0 PC5/TCMP1 PC6/RDI PC7/TDO PVDD2 PVSS2 20 21 PE7 PE6 PE5 PE4 PF3 PF2 27 PF1 PF0 PE3 PE2 PE1 PE0 34 33 PVSS1 14 40
PA5 PA4 PA3 PA2 PA1 PA0 PVDD1
Figure 1-2. MC68HC(7)05H12 Pin Assignments (52-pin PLCC package)
General Release Specification 20 General Description
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Description Functional Pin Description
1.6 Functional Pin Description
The following paragraphs give a description of the general function of each pin.
1.6.1 VDD and VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground.
1.6.2 AVDD AVDD is a separate supply pin providing power to the A/D converter.
1.6.3 OSC1, OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. A crystal connected across these pins or an external signal connected to OSC1 provides the oscillator clock. The frequency, fOSC, of the oscillator or external clock source is divided by two or eight (slow mode) to produce the internal operating frequency, fOP.
1.6.4 RESET This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. The RESET pin has an internal pulldown device that pulls the RESET pin low when there is an internal COP watchdog reset, power-on reset (POR), illegal address reset, or an internal low voltage reset. Refer to Section 5 Resets. The RESET pin contains an internal pullup device.
1.6.5 IRQ/VPP The interrupt triggering sensitivity of this pin can be programmed as falling edge sensitive or falling edge and low level sensitive.The IRQ pin
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA General Description
General Release Specification 21
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description REQUIRED
contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 4 Interrupts for more details on the interrupts. IRQ/VPP is also the EPROM programming power pin.
1.6.6 PA0-PA7/Keyboard Interrupt These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. The eight I/O lines are shared with the keyboard interrupt function. See Section 7 Input/Output Ports for more details on the I/O ports.
AGREEMENT
1.6.7 PB0-PB7/ECLK, MISO, MOSI, SCK These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. See Section 7 Input/Output Ports for more details on the I/O ports. The port pins PB5-PB7 are shared with the SPI system (MISO, MOSI, SCK). See Section 10 Serial Peripheral Interface (SPI) for more details on the operation of the SPI. Pin PB2 is shared with the internal system clock ECLK. See Section 2.3.1 System Control Register.
NON-DISCLOSURE
1.6.8 PC0-PC7/TCAP0-3, TCMP0-1, RDI, TDO These eight I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. See Section 7 Input/Output Ports for more details on the I/O ports. The port pins PC0-PC5 are shared with the 16-bit timer (TCAP0-3, TCMP0-1). See Section 9 16-Bit Timers for more details on the operation of the 16-bit timers. The port pins PC6 and PC7 are shared with the SCI system (RDI and TDO). Refer to Section 11 Serial Communications Interface (SCI).
General Release Specification 22 General Description
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Description Functional Pin Description
1.6.9 PD0-PD3/AN0-AN3 These four input only lines comprise port D. See Section 7 Input/Output Ports for more details on the I/O ports. When the A/D converter is active, one of the 4 input lines may be selected by the A/D multiplexer for conversion. See Section 12 Analog to Digital Converter for more details on the operation of the A/D subsystem.
1.6.10 VREFH This pin provides the positive reference voltage for the A/D converter. VSS provides the negative reference voltage for the A/D converter.
1.6.11 PE0-PE7 These eight output only lines comprise port E. See Section 7 Input/Output Ports for more details on the I/O ports. The eight lines are shared with four PWM H-bridge driver pairs. The outputs are formed by special power drivers. See Section 14 Pulse Width Modulator (PWM) for more details on the PWM subsystem.
1.6.12 PF0-PF3 These four output only lines comprise port F. See Section 7 Input/Output Ports for more details on the I/O ports. The four lines are shared with four PWM channels. The outputs are formed by special power drivers. See Section 14 Pulse Width Modulator (PWM) for more details on the PWM subsystem.
1.6.13 PVDD1, PVSS1, PVDD2, PVSS2 Power is supplied to the power drivers through PVDD and PVSS. PVDD1 and PVSS1 are the supply pins for PE0-3 and PF0-1 and PVDD2 and PVSS2 are the supply pins for PE4-7 and PF2-3. The VSS pin and the PVSS1 and PVSS2 pins are connected internally.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA General Description
General Release Specification 23
NON-DISCLOSURE
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REQUIRED
General Description REQUIRED NON-DISCLOSURE
General Release Specification 24 General Description
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MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 2. Memory
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 2.5 2.6 2.7 2.8 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 User EPROM (for the 705 version only) . . . . . . . . . . . . . . . . . . 35 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Introduction
The MC68HC(7)05H12 has a 16K byte memory map consisting of registers (for I/O, control and status), user RAM, user ROM (or EPROM), EEPROM, monitor ROM, and reset and interrupt vectors as shown in Figure 2-1.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 25
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
$0000 $004F $0050
I/O registers 80 bytes User RAM 256 bytes
Stack RAM 64 bytes
$00C0 $00FF
AGREEMENT
$014F $0150 $03FF $0400 $04FF $0500 $0FFF $1000 $3EFF $3F00 $3FEF $3FF0 $3FFF
Unused 688 bytes User EEPROM 256 bytes Unused 2816 bytes User ROM 12032 bytes Monitor ROM 240 bytes User vectors 16 bytes
Figure 2-1. MC68HC(7)05H12 Memory Map
2.3 Registers NON-DISCLOSURE
The I/O and control registers reside in locations $0000-$004F. The overall organization of these registers is shown in Figure 1-2. The bit assignments for each register are shown in Figure 2-3, Figure 2-4, Figure 2-5, Figure 2-6, and Figure 2-7.
General Release Specification 26 Memory
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Memory Registers
Addr
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026
Register Name
Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port C Control Register Core Timer Counter (CTCR) Unused Unused Unused Port A Interrupt Edge Port A Interrupt Control Port A Interrupt Status PWM Data 0 PWM Data 1 PWM Data 2 PWM Data 3 PWM Data 4 PWM Data 5 PWM Data 7 PWM Control/Sign PWM Channel Enable PWM Channel Polarity Unused EEPROM Control RESERVED for 705 version Unused TEST Timer1 Capture 1 High Timer1 Capture 1 Low Timer1 Compare 1 High Timer1 Compare 1 Low Timer1 Capture 2 High Timer1 Capture 2 Low Timer1 Compare 2 High PWM Data 6 Core Timer Control/Status (CTCSR)
Figure 2-2. I/O Register Summary
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 27
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
Addr
$0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F
Register Name
Timer1 Compare 2 Low Timer1 Counter High Timer1 Counter Low Timer1 Alternate Counter High Timer1 Alternate Counter Low Timer1 Control 1 Timer1 Control 2 Timer1 Status Unused Timer2 Capture 1 High Timer2 Capture 1 Low Timer2 Compare 1 High Timer2 Compare 1 Low Timer2 Capture 2 High Timer2 Capture 2 Low Timer2 Compare 2 High Timer2 Compare 2 Low Timer2 Counter High Timer2 Counter Low Timer2 Alternate Counter High Timer2 Alternate Counter Low Timer2 Control 1 Timer2 Control 2 Timer2 Status Unused Port E Data Register Port E Mismatch Register Port F Data Register Port F Mismatch Register SPI Control SPI Status SPI Data I/O SCI SCDAT SCI SCCR1 SCI SCCR2 SCI SCSR SCI BAUD Unused System Control Register A/D DATA A/D STATUS/CTL
NON-DISCLOSURE
AGREEMENT
Figure 2-2. I/O Register Summary
General Release Specification 28 Memory MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Memory Registers
Addr
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
Register
Port A Data Port B Data Port C Data Port D Data Port A Data Direction Port B Data Direction Port C Data Direction Port C Control CTSCR CTCR Unimplemented Unimplemented Unimplemented PAIED PAICR PAISR
R/W
R W R W R W R W R W R W R W R W R W R W R W W R W R W R W R W R
Bit 7
PA7 PB7 PC7 0
Bit 6
PA6 PB6 PC6 0
Bit 5
PA5 PB5 PC5 0
Bit 4
PA4 PB4 PC4 0
Bit 3
PA3 PB3 PC3 PD3 DDRA3 DDRB3 DDRC3 0 0 RTOF bit 3
Bit 2
PA2 PB2 PC2 PD2 DDRA2 DDRB2 DDRC2 0 0 RTIF bit 2
Bit 1
PA1 PB1 PC1 PD1 DDRA1 DDRB1 DDRC1 0
Bit 0
PA0 PB0 PC0 PD0 DDRA0 DDRB0 DDRC0 0
DDRA7 DDRB7 DDRC7 0 TOF bit 7
DDRA6 DDRB6 DDRC6 0 RTIF bit 6
DDRA5 DDRB5 DDRC5 TCMP1 TOFE bit 5
DDRA4 DDRB4 DDRC4 TCMP0 RTIE bit 4
RT1 bit 1
RT0 bit 0
EDGE7 PAIE7 PAIF7
EDGE6 PAIE6 PAIF6
EDGE5 PAIE5 PAIF5
EDGE4 PAIE4 PAIF4
EDGE3 PAIE3 PAIF3
EDGE2 PAIE2 PAIF2
EDGE1 PAIE1 PAIF1
EDGE0 PAIE0 PAIF0
Figure 2-3. I/O Registers $0000-$000F
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 29
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
Addr
$0010 $0011 $0012 $0013 $0014
Register
PWM Data 0 PWM Data 1 PWM Data 2 PWM Data 3 PWM Data 4 PWM Data 5 PWM Data 6 PWM Data 7 PWMCTL PWMEN PWMPOL Unimplemented EEPCR Reserved for 705 version Unimplemented TEST
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 0 PWMRS PWME7 PPOL7
Bit 6
bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 PWMC3 PWME6 PPOL6
Bit 5
bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 PWMC2 PWME5 PPOL5
Bit 4
bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 PWMC1 PWME4 PPOL4
Bit 3
bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 SIGN3 PWME3 PPOL3
Bit 2
bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 SIGN2 PWME2 PPOL2
Bit 1
bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 SIGN1 PWME1 PPOL1
Bit 0
bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 SIGN0 PWME0 PPOL0
AGREEMENT NON-DISCLOSURE
$0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
0
0
0
EEOSC
ER1
EER0
EELAT
EEPGM
0
0
0
0
0
0
0
0
Figure 2-4. I/O Registers $0010-$001F
General Release Specification 30 Memory
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Memory Registers
Addr
$0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F
Register
Timer 1 Input Capture1 High Timer 1 Input Capture1 Low Timer 1 Output Compare1 High Timer 1 Output Compare1 Low Timer 1 Input Capture2 High Timer 1 Input Capture2 Low Timer 1 Output Compare2 High Timer 1 Output Compare2 Low Timer 1 Counter High Timer 1 Counter Low Timer 1 Alternate Counter High Timer 1 Alternate Counter Low Timer 1 Control 1 Timer 1 Control 2 Timer 1 Status Unimplemented
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
bit 15 bit 7
Bit 6
bit 14 bit 6
Bit 5
bit 13 bit 5
Bit 4
bit 12 bit 4
Bit 3
bit 11 bit 3
Bit 2
bit 10 bit 2
Bit 1
bit 9 bit 1
Bit 0
bit 8 bit 0
bit 15 bit 7 bit 15 bit 7
bit 14 bit 6 bit 14 bit 6
bit 13 bit 5 bit 13 bit 5
bit 12 bit 4 bit 12 bit 4
bit 11 bit 3 bit 11 bit 3
bit 10 bit 2 bit 10 bit 2
bit 9 bit 1 bit 9 bit 1
bit 8 bit 0 bit 8 bit 0
bit 15 bit 7 bit 15 bit 7 bit 15 bit 7
bit 14 bit 6 bit 14 bit 6 bit 14 bit 6
bit 13 bit 5 bit 13 bit 5 bit 13 bit 5
bit 12 bit 4 bit 12 bit 4 bit 12 bit 4
bit 11 bit 3 bit 11 bit 3 bit 11 bit 3
bit 10 bit 2 bit 10 bit 2 bit 10 bit 2
bit 9 bit 1 bit 9 bit 1 bit 9 bit 1
bit 8 bit 0 bit 8 bit 0 bit 8 bit 0
ICI1E 0 IC1F
ICI2E 0 IC2F
OCI1E OC2IE OC1F
TOIE 0 TOF
CO1E CO2E TCAP1
IEDG1 0 TCAP2
IEDG2 0 OC2F
OLVL1 OLVL2 0
Figure 2-5. I/O Registers $0020-$002F
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 31
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
Addr
$0030
Register
Timer 2 Input Capture1 High
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
bit 15 bit 7
Bit 6
bit 14 bit 6
Bit 5
bit 13 bit 5
Bit 4
bit 12 bit 4
Bit 3
bit 11 bit 3
Bit 2
bit 10 bit 2
Bit 1
bit 9 bit 1
Bit 0
bit 8 bit 0
Timer 2 Input Capture1 $0031 Low $0032 $0033 $0034 Timer 2 Output Compare1 High Timer 2 Output Compare1 Low Timer 2 Input Capture2 High
bit 15 bit 7 bit 15 bit 7
bit 14 bit 6 bit 14 bit 6
bit 13 bit 5 bit 13 bit 5
bit 12 bit 4 bit 12 bit 4
bit 11 bit 3 bit 11 bit 3
bit 10 bit 2 bit 10 bit 2
bit 9 bit 1 bit 9 bit 1
bit 8 bit 0 bit 8 bit 0
AGREEMENT
Timer 2 Input Capture2 $0035 Low $0036 $0037 $0038 $0039 $003A $003B Timer 2 Output Compare2 High Timer 2 Output Compare2 Low Timer 2 Counter High Timer 2 Counter Low Timer 2 Alternate Counter High Timer 2 Alternate Counter Low Timer 2 Control 1 Timer 2 Control 2 Timer 2 Status Unimplemented
bit 15 bit 7 bit 15 bit 7 bit 15 bit 7 ICI1E 0 IC1F
bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 ICI2E 0 IC2F
bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 OCI1E OC2IE OC1F
bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 TOIE 0 TOF
bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 CO1E CO2E TCAP1
bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 IEDG1 0 TCAP2
bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 IEDG2 0 OC2F
bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 OLVL1 OLVL2 0
NON-DISCLOSURE
$003C $003D $003E $003F
Figure 2-6. I/O Registers $0030-$003F
General Release Specification 32 Memory
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Memory Registers
Addr
$0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F
Register
Port E Data Port E Mismatch Port F Data Port F Mismatch SPI Control SPI Status SPI Data SCI Data SCI Control 1 SCI Control 2 SCI Status SCI BAUD Unimplemented System Control A/D Data A/D Status/Control
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
PE7 bit 7 0 0
Bit 6
PE6 bit 6 0 0
Bit 5
PE5 bit 5 0 0
Bit 4
PE4 bit 4 0 0
Bit 3
PE3 bit 3 PF3 bit 3 CPOL 0
Bit 2
PE2 bit 2 PF2 bit 2 CPHA 0
Bit 1
PE1 bit 1 PF1 bit 1 SPR1 0
Bit 0
PE0 bit 0 PF0 bit 0 SPR0 0
SPIE SPIF
SPE WCOL
DOD 0
MSTR 0
bit 7 bit 7 R8
bit 6 bit 6 T8 TCIE TC
bit 5 bit 5 0
bit 4 bit 4 M ILIE IDLE
bit 3 bit 3 WAKE TE OR 0 RCKB
bit 2 bit 2 0
bit 1 bit 1 0
bit 0 bit 0 0
TIE TDRE 0 TCLR
RIE RDRF
RE NF
RWU FE
SBK 0
SPP
SCP1
SCP0
SCR2
SCR1
SCR0
0 bit 7 COCO
0 bit 6
0 bit 5
SC bit 4 0
IRQ bit 3
0 bit 2
0 bit 1
ECLK bit 0
ADRC
ADON
CH3
CH2
CH1
CH0
Figure 2-7. I/O Registers $0040-$004F
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 33
NON-DISCLOSURE
AGREEMENT
REQUIRED
Memory REQUIRED
2.3.1 System Control Register The MC68HC(7)05H12 contains a system control register which is located at $004D. This register is used to control the IRQ interrupt sensitivity, the bus frequency, and the external availability of the internal bus clock.
$004D Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 SC IRQ 4 3 2 0 1 0 ECLK Bit 0
AGREEMENT
Figure 2-8. System Control Register (SYSCR) SC -- System Clock Option After power on reset the internal bus frequency fOP is = fOSC/2. The SC bit allows the user to reduce the system speed to fOSC/8. 1 = fOP = fOSC/8 (Slow Mode) 0 = fOP = fOSC/2 IRQ -- IRQ Sensitivity IRQ edge or level sensitive 1 = IRQ input edge and level sensitive 0 = IRQ input edge sensitive ECLK -- Internal System Clock Available The ECLK bit makes the internal system clock (bus frequency fOP) available to the user. Refer to Section 7.4 Port B for more details. 1 = The PB2/ECLK pin provides the internal system clock independently of the value of the port B data direction register 0 = The internal system clock is not available, the PB2/ECLK pin is an ordinary I/O port line
NON-DISCLOSURE
General Release Specification 34 Memory
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Memory RAM
2.4 RAM
The user RAM consists of 256 bytes ranging from $0050 to $014F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. The stack is located in the middle of the RAM address space. Data written to addresses within the stack address range could be overwritten during stack activity.
2.5 ROM
The 12032 bytes of the user ROM are located from $1000 to $3EFF, plus 16 bytes of user vectors from $3FF0 to $3FFF.
2.6 Monitor ROM
The monitor ROM ranges from $3F00 to $3FEF. The vectors for the bootloader are located from $3FE0 to $3FEF.
The 12032 bytes of the user EPROM are located from $1000 to $3EFD, including two bytes of mask option registers (MOR) at $3EFE and $3EFF, plus 16 bytes of user vectors from $3FF0 to $3FFF. Refer to Section 15 EPROM for programming details.
2.8 EEPROM
This device contains 256 bytes of EEPROM. Programming the EEPROM is performed by the user on a single-byte basis by manipulating the EEPROM control register, located at address $001C. Refer to Section 13 EEPROM for programming details.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Memory
General Release Specification 35
NON-DISCLOSURE
2.7 User EPROM (for the 705 version only)
AGREEMENT
REQUIRED
Memory REQUIRED NON-DISCLOSURE
General Release Specification 36 Memory
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 3. CPU and Instruction Set
3.1 Contents
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 3.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.7 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . 46 3.7.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 47 3.7.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 37
NON-DISCLOSURE
3.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AGREEMENT
REQUIRED
CPU and Instruction Set REQUIRED 3.2 Introduction
This chapter describes the CPU registers and the HC05 instruction set.
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 A 0 ACCUMULATOR (A)
AGREEMENT
7 X
0 INDEX REGISTER (X)
15 0 0 0 0 0 0 0 0 1
6 1
5 SP
0 STACK POINTER (SP)
15
10 PCH
8
7 PCL
0 PROGRAM COUNTER (PC)
NON-DISCLOSURE
7 1 1
5 1
4 H I N Z
0 C CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG
Figure 3-1. Programming Model
General Release Specification 38 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set CPU Registers
3.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and nonarithmetic operations.
Bit 7 Reset:
6
5
4
3
2
1
Bit 0
Unaffected by reset
Figure 3-2. Accumulator 3.3.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand.
Bit 7 Reset:
6
5
4
3
2
1
Bit 0
Unaffected by reset
Figure 3-3. Index Register The 8-bit index register can also serve as a temporary data storage location.
3.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer is preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Bit 15 14 0 Reset 0 0 0
13 0 0
12 0 0
11 0 0
10 0 0
9 0 0
8 0 0
7 1 1
6 1 1
5
4
3
2
1
Bit 0
1
1
1
1
1
1
Figure 3-4. Stack Pointer
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set General Release Specification 39
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The ten most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations. An interrupt uses five locations.
3.3.4 Program Counter
AGREEMENT
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Bit 15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
NON-DISCLOSURE
- Reset -
- - Loaded with vector from $3FFE AND $3FFF
Figure 3-5. Program Counter 3.3.5 Condition Code Register The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register.
Bit 7 1 Reset 1 6 1 1 5 1 1 4 H U 3 I 1 2 N U 1 C U Bit 0 Z U
Figure 3-6. Condition Code Register
General Release Specification 40 CPU and Instruction Set MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set CPU Registers
Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
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CPU and Instruction Set REQUIRED 3.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations.
AGREEMENT
3.5 Instruction Set Overview
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
NON-DISCLOSURE
3.6 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset
General Release Specification 42 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set Addressing Modes
* *
Indexed, 16-bit offset Relative
3.6.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
3.6.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
3.6.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
3.6.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 43
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3.6.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
AGREEMENT
3.6.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
NON-DISCLOSURE
3.6.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
General Release Specification 44 CPU and Instruction Set MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set Instruction Types
3.6.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
3.7 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
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3.7.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 3-1. Register/Memory Instructions
Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
AGREEMENT
Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator
NON-DISCLOSURE
General Release Specification 46
MC68HC(7)05H12 -- Rev. 1.0 CPU and Instruction Set MOTOROLA
CPU and Instruction Set Instruction Types
3.7.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 3-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
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3.7.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
NON-DISCLOSURE
General Release Specification 48 CPU and Instruction Set
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MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set Instruction Types
Table 3-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL
BRCLR BRN BRSET BSR JMP JSR
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 49
NON-DISCLOSURE
BRA
AGREEMENT
REQUIRED
CPU and Instruction Set REQUIRED
3.7.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 3-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
AGREEMENT
Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set
NON-DISCLOSURE
General Release Specification 50 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
CPU and Instruction Set Instruction Types
3.7.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 3-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI SWI TAX TXA
WAIT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
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CPU and Instruction Set REQUIRED 3.8 Instruction Set Summary
Table 3-6. Instruction Set Summary
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
AGREEMENT
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
A9 ii 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 A4 ii 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
-- -- --
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
-- --
NON-DISCLOSURE
ff dd
Arithmetic Shift Right
b7 b0
C
-- --
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ----------
General Release Specification 52 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Cycles
Effect on CCR
Operand
CPU and Instruction Set Instruction Set Summary
Table 3-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
H I NZC
---------- ----------
REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
2F 2E
rr rr
Bit Test Accumulator with Memory Byte
(A) (M)
-- -- --
A5 ii 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Cycles
3 3 6 2 2
Effect on CCR
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -- -- -- -- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -- -- -- -- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n opr
Set Bit n
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 53
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AGREEMENT
REQUIRED
Operand
CPU and Instruction Set REQUIRED
Table 3-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
AGREEMENT
Compare Accumulator with Memory Byte
(A) - (M)
-- --
A1 ii 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
-- --
1
ff
Compare Index Register with Memory Byte
(X) - (M)
-- --
A3 ii 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
NON-DISCLOSURE
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
-- -- --
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
-- -- --
A8 ii 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
-- -- --
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2
General Release Specification 54 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Cycles
5 3 3 6 5
Effect on CCR
Operand
CPU and Instruction Set Instruction Set Summary
Table 3-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X
Operation
Description
H I NZC
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
Jump to Subroutine
----------
DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 A6 ii 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2
Load Index Register with Memory Byte
X (M)
-- -- --
Logical Shift Left (Same as ASL)
C b7 b0
0
-- --
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
-- --
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
-- -- --
AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 39 49 59 69 79 dd 5 3 3 6 5
Rotate Byte Left through Carry Bit
C b7 b0
-- --
ff
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 55
NON-DISCLOSURE
ff
AGREEMENT
Load Accumulator with Memory Byte
A (M)
-- -- --
Cycles
Effect on CCR
REQUIRED
Operand
CPU and Instruction Set REQUIRED
Table 3-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Right through Carry Bit
b7 b0
C
-- --
DIR INH INH IX1 IX INH
36 46 56 66 76 9C
dd
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
AGREEMENT
RTI
Return from Interrupt

INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
-- --
A2 ii 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
NON-DISCLOSURE
Store Accumulator in Memory
M (A)
-- -- --
B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 A0 ii 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
Store Index Register In Memory
M (X)
-- -- --
Subtract Memory Byte from Accumulator
A (A) - (M)
----
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
10
TAX
Transfer Accumulator to Index Register
INH
97
General Release Specification 56 CPU and Instruction Set
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Cycles
5 3 3 6 5 2 9 6 2
Effect on CCR
Operand
CPU and Instruction Set Instruction Set Summary
Table 3-6. Instruction Set Summary (Continued)
Address Mode Opcode Source Form
TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operation
Description
H I NZC
Test Memory Byte for Negative or Zero
(M) - $00
----
--
DIR INH INH IX1 IX INH INH
3D 4D 5D 6D 7D 9F 8F
dd
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
A (X)
---------- -- 0 ------
Cycles
4 3 3 5 4 2 2
Effect on CCR
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA CPU and Instruction Set
General Release Specification 57
NON-DISCLOSURE
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
AGREEMENT
REQUIRED
Operand
NON-DISCLOSURE
Table 3-7. Opcode Map
Branch REL DIR 3
SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB
AGREEMENT
REQUIRED
CPU and Instruction Set
General Release Specification
Read-Modify-Write INH INH IX1 IX 7 8 9 A B C D E F
3
58
Control INH INH IMM DIR IX1 IX
MSB LSB
Bit Manipulation DIR DIR 2 4 5 6
Register/Memory EXT IX2
MSB LSB
0
1
0
0 1 2 3 4 5 6 7 8 9 A B C D E F
1
2
3
4
5
6
7
8
CPU and Instruction Set
0
LSB of Opcode in Hexadecimal
9
A
B
C
D
E
F
5 5 3 5 3 3 6 5 9 2 3 4 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI SUB SUB SUB 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 6 2 3 4 BRCLR0 BCLR0 BRN RTS CMP CMP CMP 3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 11 2 3 4 BRSET1 BSET1 BHI MUL SBC SBC SBC 3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 10 2 3 4 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 3 4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 5 5 3 2 3 4 BRCLR2 BCLR2 BCS/BLO BIT BIT BIT 3 DIR 2 DIR 2 REL 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 3 4 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 4 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 2 3 4 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL CLC EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 2 3 4 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 2 3 4 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 2 2 3 4 BRCLR5 BCLR5 BMI SEI ADD ADD ADD 3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 2 3 BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 5 5 3 4 3 3 5 4 2 6 5 6 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 5 5 3 2 3 4 BRSET7 BSET7 BIL LDX LDX LDX 3 DIR 2 DIR 2 REL 2 IMM 2 DIR 3 EXT 3 5 5 3 5 3 3 6 5 2 2 4 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3
5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
MSB of Opcode in Hexadecimal
MC68HC(7)05H12 -- Rev. 1.0
INH = InherentREL = Relative IMM = ImmediateIX = Indexed, No Offset DIR = DirectIX1 = Indexed, 8-Bit Offset EXT = ExtendedIX2 = Indexed, 16-Bit Offset
MOTOROLA
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
General Release Specification -- MC68HC(7)05H12
Section 4. Interrupts
4.1 Contents
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 External Interrupt (IRQ/Keyboard) . . . . . . . . . . . . . . . . . . . . . . 63 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16-Bit Timer1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16-Bit Timer2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Interrupts
General Release Specification 59
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED 4.2 Introduction
The MCU can be interrupted eight different ways: 1. Nonmaskable Software Interrupt Instruction (SWI) 2. External Asynchronous Interrupt (IRQ) 3. External Keyboard Wakeup on Port A 4. Internal 8 bit Timer Interrupt (CTIMER) 5. Internal 16-bit Timer1 Interrupt (TIMER1) 6. Internal 16-bit Timer2 Interrupt (TIMER2) 7. Internal Serial Communications Interface Interrupt (SCI) 8. Internal Serial Peripheral Interface Interrupt (SPI)
AGREEMENT
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set, then the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF0 to $3FFF as defined in Table 4-1.
NON-DISCLOSURE
General Release Specification 60 Interrupts
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Interrupts CPU Interrupt Processing
Table 4-1. Reset/Interrupt Vector Addresses
Function Source
Power-On Logic Reset Software Interrupt (SWI) External Interrupt / KEY wakeup Core Timer Interrupts 16-Bit Timer 1 Interrupts RESET Pin COP Watchdog User Code IRQ Pin PTA KEY Pins RTIF Bit TOF Bit ICF Bits OCF Bits TOF Bit ICF Bits 16-Bit Timer 2 Interrupts SPI Interrupts OCF Bits TOF Bit SPIF Bit MODF Bit TDRE Bit TC Bit SCI Interrupts RDRF Bit OR Bit IDLE Bit None None PAIE Bits RTIE Bit TOFE Bit ICIE Bits OCIE Bits TOIE Bit ICIE Bits OCIE Bits TOIE Bit SPIE TCIE Bit RIE Bit ILIE Bit I Bit 7 $3FF0-$3FF1 I Bit 6 $3FF2-$3FF3 I Bit 5 $3FF4-$3FF5 I Bit 4 $3FF6-$3FF7 I Bit 3 $3FF8-$3FF9 None I Bit Same Priority As Instruction 2 $3FFC-$3FFD $3FFA-$3FFB None None 1 $3FFE-$3FFF
Local Mask
Global Mask
Priority (1 = Highest)
Vector Address
The M68HC05 CPU does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tCYC secs An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Interrupts
General Release Specification 61
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED
FROM RESET
Y
I-BIT IN CCR SET? N IRQ/KEY EXTERNAL INTERRUPT N Y CLEAR IRQ REQUEST LATCH
AGREEMENT
INTERNAL 8 BIT CORE TIMER INTERRUPT N INTERNAL 16 BIT TIMER1 INTERRUPT N INTERNAL 16 BIT TIMER2 INTERRUPT N INTERNAL SPI INTERRUPT N INTERNAL SCI INTERRUPT N
Y
Y
Y
Y
NON-DISCLOSURE
STACK PC,X,A,CCR Y SET I BIT IN CC REGISTER LOAD PC FROM APPROPRIATE VECTOR Y
FETCH NEXT INSTRUCTION
SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR,A,X,PC EXECUTE INSTRUCTION
Figure 4-1. Interrupt Processing Flowchart
General Release Specification 62 Interrupts MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Interrupts Reset Interrupt Sequence
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $3FFE and $3FFF. The I-bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in Section 5 Resets.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched, or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
All hardware interrupts except reset are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware interrupts (external, internal) which are explained in the following sections.
4.7 External Interrupt (IRQ/Keyboard)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $3FFA and $3FFB.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Interrupts
General Release Specification 63
NON-DISCLOSURE
4.6 Hardware Interrupts
AGREEMENT
REQUIRED
Interrupts REQUIRED
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitiveonly trigger can be implemented by software.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I bit is cleared. The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the Port A keyboard wakeup interrupts. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs.
AGREEMENT
4.8 8-Bit Timer Interrupt
This timer can create two types of interrupts. A timer overflow interrupt will occur whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real time interrupt will occur whenever the programmed time elapses and the enable bit RTIE is set. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $3FF8 and $3FF9.
NON-DISCLOSURE
4.9 16-Bit Timer1 Interrupt
There are five different timer interrupt flags that cause a 16-bit timer1 interrupt whenever they are set and enabled. The interrupt flags are in the timer1 status register (TSR), and the enable bits are in the timer1 control register1 (TCR1). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3FF6 and $3FF7.
4.10 16-Bit Timer2 Interrupt
There are five different timer interrupt flags that cause a 16-bit timer2 interrupt whenever they are set and enabled. The interrupt flags are in the timer2 status register (TSR), and the enable bits are in the timer2 control register1 (TCR1). Any of these interrupts will vector to the same
General Release Specification 64 Interrupts
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Interrupts SCI Interrupt
interrupt service routine, located at the address specified by the contents of memory location $3FF4 and $3FF5.
4.11 SCI Interrupt
There are five different interrupt flags (TDRE, TC, OR, RDRF, IDLE) that will cause an SCI interrupt whenever they are set and enabled. These five interrupt flags are found in the five most significant bits of the SCI status register SCSR. The actual processor interrupt is generated only if the I-bit in the condition code register is clear and the enable bit in the serial communications control register 2 (SCCR2) is enabled. The SCI interrupt causes the program counter to vector to the address pointed to by memory locations $3FF2-$3FF3 which contain the start address of the interrupt service routine. Software in the SCI interrupt service routine must determine the priority and cause of the SCI interrupt by examining the interrupt flags and the status bits in the serial communications status register (SCSR).
4.12 SPI Interrupt
There are two different SPI interrupt flags that cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF0 and $3FF1.
4.13 WAIT Mode
All modules that are capable of generating interrupts in WAIT mode will be allowed to do so if the module is configured properly. The I-bit is automatically cleared when WAIT mode is entered. Interrupts detected on port A are recognized in WAIT modes.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Interrupts
General Release Specification 65
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED NON-DISCLOSURE
General Release Specification 66 Interrupts
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 5. Resets
5.1 Contents
5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . . 70 5.6.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 COP During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . 71 5.6.4 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.7 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 Low Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8.1 LVR Operation in WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Introduction
The MCU can be reset from five sources: one external input and four internal restart conditions. The RESET pin is an input with a Schmitt trigger. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail. The RESET pin contains an internal pullup device.
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Resets General Release Specification 67
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED
threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the RST signal and reset the CPU and peripherals. When the RESET pin goes high, the MCU will resume operation on the following cycle.
NOTE:
Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified.
The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown that is activated by any reset source. This RESET pulldown device will be asserted for 3-4 cycles of the internal clock, fOP, or as long as an internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will be turned on for the 3-4 internal clock cycles.
AGREEMENT
5.4 Internal Resets
The four internally generated resets are the initial power-on reset function, the COP Watchdog Timer reset, the illegal address detector, and the low voltage reset. All internal resets will also assert (pull to logic zero) the external RESET pin for the duration of the reset or 3-4 internal clock cycles, whichever is longer.
VDD INTERNAL PULLUP RESET PIN INTERNAL RESETS INTERNAL RESET LOGIC
NON-DISCLOSURE
Figure 5-1. Internal Resets
General Release Specification 68 Resets
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
MOTOROLA
POR THRESHOLD (TYP. 1-2V) 4 tcyc 3FFE 3FFF NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC NEW PCH PCH tRL 3 NEW PCL OP CODE PCL OP CODE
V DD
0v
OSC1 2
MC68HC(7)05H12 -- Rev. 1.0
4064 tcyc
INTERNAL PROCESSOR CLOCK 1
INTERNAL ADDRESS BUS 1
Resets
INTERNAL DATA BUS 1
RESET
NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. VDD must fall to a level lower than VPOR in order to recognized as a power on reset. If LVR is enabled, VDD must fall below the LVR Power Off Reset Voltage VROFF.
Figure 5-2. RESET and POR Timing Diagram
Resets Internal Resets
General Release Specification
69
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED 5.5 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will activate the RESET pin pulldown device connected to the pin. VDD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD.
AGREEMENT
5.6 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Regardless of an internal or external reset, the MCU comes out of a COP reset according to the pin conditions that determine mode selection. The COP reset function is enabled or disabled by the Mask option (COP) and is verified during production testing. The COP Watchdog reset will activate the internal pulldown device connected to the RESET pin.
NON-DISCLOSURE
5.6.1 Resetting the COP Preventing a COP reset is done by writing a `0' to the COPR bit. This action will reset the counter and begin the time-out period again. The COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return user data programmed at that location.
General Release Specification 70 Resets
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Resets Computer Operating Properly Reset (COPR)
5.6.2 COP During WAIT Mode The COP will continue to operate normally during WAIT mode. The system should be configured to pull the device out of WAIT mode periodically and reset the COP by writing to the COPR bit to prevent a COP reset.
5.6.3 COP Watchdog Timer Considerations The COP Watchdog Timer is active in User Mode if enabled by the Mask option (COP). If the COP Watchdog Timer is selected, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP Watchdog should be disabled for a system that must have intentional uses of the WAIT Mode for periods longer than the COP time-out period.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Resets
General Release Specification 71
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED
5.6.4 COP Register The COP register is shared with the MSB of a user interrupt vector as shown in Figure 5-3. Reading this location will return whatever user data has been programmed at this location. Writing a `0' to the COPR bit in this location will clear the COP watchdog timer.
$3FF0
Bit 7
6
5
4
3
2
1
Bit 0
AGREEMENT
Read: Write: Reset: COPR
Figure 5-3. COP Watchdog Timer Location Register (COPR)
5.7 Illegal Address Reset
An illegal address reset is generated when the CPU attempts to fetch an instruction from either unimplemented address space ($0150 to $03FF, $0500 to $0FFF), Monitor ROM ($3F00 to $3FEF) or I/O address space ($0000 to $004F). The illegal address reset will activate the internal pulldown device connected to the RESET pin.
NON-DISCLOSURE
NOTE:
No RTS, RTI or JMP,X instruction should be placed at the end of a memory block (RAM $014F, EEPROM $04FF, User ROM $3EFF) since this results in an illegal address reset.
5.8 Low Voltage Reset (LVR)
The internal low voltage (LVR) reset is generated when VDD falls below the LVR threshold VROFF and will be release following a POR delay starting when VDD rises above VRON. The LVR threshold is tested to be above the minimum operating voltage of the microcontroller and is intended to assure that the CPU will be held in reset when the VDD supply voltage is below reasonable operating limits. A mask option is
General Release Specification 72 Resets
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Resets Low Voltage Reset (LVR)
provided to disable the LVR when the device is expected to normally operate at low voltages. Note that the VDD rise and fall slew rates must be within the specification for proper LVR operation. If the specification is not met, the circuit will operate properly following a delay of VDD/Slew rate. The LVR will generate the RST signal which will reset the CPU and other peripherals. The low voltage reset will activate the internal pulldown device connected to the RESET pin. If any other reset function is active at the end of the LVR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end.
VDD
VRON VROFF
HYSTERESIS
RESET
Figure 5-4. Low Voltage Reset
5.8.1 LVR Operation in WAIT If enabled, the LVR supply voltage sense option is active during WAIT. Any reset source can bring the MCU out of WAIT mode.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Resets
General Release Specification 73
NON-DISCLOSURE
NOTE:
An external capacity at the RST pin increases the reaction time for the generation of the internal reset and allows VDD drops. Refer to Figure 5-1.
AGREEMENT
REQUIRED
Resets REQUIRED NON-DISCLOSURE
General Release Specification 74 Resets
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Operating Modes Contents
General Release Specification -- MC68HC(7)05H12
Section 6. Operating Modes
6.1 Contents
6.2 6.3 6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.2 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.3 Slow Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2 Introduction
The normal operating mode of the MC68HC(7)05H12 is user (or single chip) mode. There is also a monitor (or bootloader) mode, primarily for programming and evaluation purpose. In addition to these modes, there are three low power modes which may be entered and exited at will from user mode: WAIT, Data Retention and Slow Mode. Table 6-1 shows the conditions required to enter the modes of operation on the rising edge of RESET, were VTST = 2 x VDD. Table 6-1. Operating Mode Entry Conditions
IRQ
VSS to VDD VTST
PB0
VSS to VDD VDD
Mode
User Monitor
6.3 User Mode
This is the intended mode of operation for executing user firmware. All user mode functions are explained in this specification.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Operating Modes General Release Specification 75
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operating Modes REQUIRED 6.4 Monitor Mode
This mode is used for programming the on-chip EPROM (705 version) and for the communication with a host computer via a standard RS-232 interface.
6.5 Low Power Modes
The MC68HC(7)05H12 is capable of running in one of several lowpower operational modes. The WAIT instruction provides a mode that reduces the power required for the MCU by stopping various internal clocks. The flow of the WAIT mode is shown in Figure 6-1.
NON-DISCLOSURE
General Release Specification 76 Operating Modes
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Operating Modes Low Power Modes
WAIT
OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED
N
Y
KEYBOARD INTERRUPT, IRQ OR CTIMER. Y
N
16B TIMER, SPI OR SCI YINTERRUPT Y
N
RESTART PROCESSOR CLOCK
1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
Figure 6-1. WAIT Flowchart 6.5.1 WAIT Mode The WAIT instruction places the MCU in a low-power consumption mode. All CPU action is suspended, but the core timer, the 16 bit timers, the SPI/SCI, the ADC, and the PWM will or can remain active. An
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Operating Modes
General Release Specification 77
NON-DISCLOSURE
AGREEMENT
RESET OR LVR
REQUIRED
Operating Modes REQUIRED
interrupt, if enabled, from the core timer or any peripheral still active in WAIT mode will cause the MCU to exit WAIT mode. During WAIT mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The core timer may be enabled to allow a periodic exit from the WAIT mode.
6.5.2 Data Retention Mode
AGREEMENT
The contents of RAM and CPU registers are retained at data retention supply voltage VDR. This is called the data retention mode where the data is held, but the device is not guaranteed to operate. The RESET pin must be held low during data-retention mode. To put the MCU into data retention mode: * * Drive RESET pin to zero. Lower the VDD voltage. The RESET pin must remain low continuously during data retention mode.
To take the MCU out of data retention mode:
NON-DISCLOSURE
* *
Return VDD to normal operating level. Return the RESET pin to logic one.
6.5.3 Slow Mode The slow mode function is controlled by the system clock option (SC bit) in the system control register. It allows the user to interconnect under software control an extra divide-by-4 between the oscillator and the internal clock driver. This feature allows all the internal operations to slow down and thus reduces power consumption. It is particularly useful when entering Wait mode. See Section 2.3.1 System Control Register.
General Release Specification 78 Operating Modes
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 7. Input/Output Ports
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.1 Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2 Port A Interrupt Edge Register . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 Port A Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . 81 7.3.4 Port A Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . 82 7.4 7.5 7.6 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.8 7.9
Port E and Port F During WAIT Mode . . . . . . . . . . . . . . . . . . . 95 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2 Introduction
In single chip mode there is a total of 40 lines arranged as three 8-bit I/O ports (ports A, B and C), one 4-bit input only port (port D), 12 output only lines arranged as one 8-bit (port E) and one 4-bit (port F) port. The I/O
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 79
NON-DISCLOSURE
7.7 Port E and Port F (Power Drivers) . . . . . . . . . . . . . . . . . . . . . . 83 7.7.1 Power Drivers for 360Air Core Driven Instruments . . . . . . 85 7.7.2 H-Bridge Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7.3 Power Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.4 Short Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.5 Port E and Port F Mismatch Registers . . . . . . . . . . . . . . . . 89 7.7.6 Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.7.7 Port E and Port F Configurations . . . . . . . . . . . . . . . . . . . . 92 7.7.8 H-Bridge Control with the PWM . . . . . . . . . . . . . . . . . . . . . 94
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
ports are programmable as either inputs or outputs under software control of the data direction registers.
NOTE:
To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port. The port A Data register is at $0000 and the port A data direction register (DDR) is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
AGREEMENT
7.3.1 Port A Keyboard Interrupt The keyboard interrupt consists of 8 individual edge-sensitive interrupts with 8 interrupt flags. The keyboard interrupt is generated by a logical OR function of the 8 interrupt flags. The interrupt inputs are connected to PA0-7. All interrupts are maskable. If the interrupt mask bit (I bit) in the condition code register is set, all interrupts are disabled. Each interrupt can individually be masked by the corresponding PAIE7-0 bits in the port A interrupt control register. The trigger edges of the interrupt lines are programmable with the EDG7-0 bits in the port A interrupt edge register. The PA0-7 input lines have no internal pull-up resistors.
NON-DISCLOSURE
General Release Specification 80 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port A
7.3.2 Port A Interrupt Edge Register
$000D Read:
Bit 7 EDGE7
6 EDGE6 0
5 EDGE5 0
4 EDGE4 0
3 EDGE3 0
2 EDGE2 0
1 EDGE1 0
Bit 0 EDGE0 0
Write: Reset: 0
Figure 7-1. Port A Interrupt Edge Register (PAIED) EDGE7-0 -- Port A Interrupt Edge These bits select the corresponding trigger edges of the interrupt lines PA7-PA0. Note that changing these bits can cause an interrupt, if the corresponding pin is `1' and the bit changes from `0' to `1' or if the corresponding pin is `0' and the bit changes from `1' to `0'. 1 = Low to high edge sensitive 0 = High to low edge sensitive
7.3.3 Port A Interrupt Control Register
$000E Read:
Bit 7 PAIE7
6 PAIE6 0
5 PAIE5 0
4 PAIE4 0
3 PAIE3 0
2 PAIE2 0
1 PAIE1 0
Bit 0 PAIE0 0
Write: Reset: 0
Figure 7-2. Port A Interrupt Control Register (PAICR) PAIE7-0 -- Port A Interrupt Enable Each of these bits enables the corresponding port A pin as interrupt line 1 = Corresponding port A interrupt enabled 0 = Corresponding port A interrupt disabled
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 81
NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
7.3.4 Port A Interrupt Status Register
$000F Read:
Bit 7 PAIF7
6 PAIF6 0
5 PAIF5 0
4 PAIF4 0
3 PAIF3 0
2 PAIF2 0
1 PAIF1 0
Bit 0 PAIF0 0
Write: Reset: 0
Figure 7-3. Port A Interrupt Status Register (PAISR)
AGREEMENT
PAIF7-0 -- Port A Interrupt Flags These flags indicate which of the port A interrupt requests is pending. The 8 interrupt flags can be reset individually if a `1' is written to the bit position. 1 = Flag set when corresponding transition is sensed (even if interrupt is disabled), writing `1' clears the flag 0 = No interrupt
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001, the port B data direction register (DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. The port pins PB5-PB7 are shared with the SPI system (MISO, MOSI, SCK). If the SPI system is enabled the pins PB5-PB7 are connected to the SPI system. Pin PB2 is shared with the internal system clock ECLK. If the ECLK bit in the system option register is set the internal system clock is available through PB2 independently of the value of the port B data direction register. Refer to Section 2.3.1 System Control Register for more information. When the ECLK bit is set to `1' the port B data direction register can still be read or written, but does not impact the ECLK function at pin PB2. When the ECLK bit is set to `1' the port B data register bit 2 loses its contents and is not accessible.
NON-DISCLOSURE
General Release Specification 82 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port C
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002, the port C data direction register (DDR) is at $0006 and the port C control register is at $0007. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Reset clears the control register. The port pins PC0-PC5 are shared with the 16-bit timers (TCAP0-3, TCMP0-1). The lines PC0-PC3 must be set to input by resetting the DDR to enable correct input capture function. If the TCMP1 or TCMP2 bit in the control register is set the pins PC5, PC4 function as output compare lines from the Timer1 system otherwise they function as I/O lines. The port pins PC6, PC7 are shared with the SCI system (RDI, TDO). If the SCI is enabled the pins PC6, PC7 are connected to the SCI system.
7.6 Port D
Port D is an 4-bit input only port which shares all of its pins with the A/D converter (AN0 through AN3). The port D data register is located at address $0003. When the A/D converter is active, one of these 4 input lines may be selected by the A/D multiplexer for conversion. A logical read of a selected input port will always return 0.
7.7 Port E and Port F (Power Drivers)
Port E is an 8-bit output only port. The port E data register is at $0040. Reset clears the data register. The eight lines are shared with four PWM H-bridge driver pairs (left and right). The outputs are formed by power drivers. The port E PWM lines can support two 360 (large angle) aircore instruments. Port F is a 4-bit output only port. The port F data register is at $0042. Reset clears the data register. The four lines are shared with four PWM channels. The outputs are formed by power drivers. The port F PWM lines can support four 90 (small angle) aircore instruments.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 83
NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
The power drivers have a separate voltage supply. PVDD1 and PVSS1 is the supply for PE0-3 and PF0-1 and PVDD2 and PVSS2 is the supply for PE4-7 and PF2-3. The power drivers contain short circuit detection and slew rate limitation for reduced RFI (EMC).
PVDD1 LEFT PWM0 RIGHT LEFT PWM1 RIGHT PE3 PVSS1 PVDD2 LEFT PWM2 RIGHT LEFT PWM3 RIGHT PE7 PVSS2 PVDD1 PWM4 PWM5 PF0 PF1 PVSS1 PVDD2 PWM6 PWM7 PF2 PF3 PVSS2 PE5 PE6 PE4 PE1 PE2 PE0
NON-DISCLOSURE
AGREEMENT
Figure 7-4. Port E and Port F (Power Drivers)
General Release Specification 84 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F (Power Drivers)
7.7.1 Power Drivers for 360Air Core Driven Instruments Two PWM H-bridge systems are used to drive a system with cross coupled coils for a dashboard instrument. A single bridge is controlled by one PWM channel in combination with a further general purpose output (GPO) channel. It is capable of driving one of the two coils of an aircore instrument. The pulse width ratio in one of the two PWM channels corresponds to the average value of the current through the coil.
PWM2 I2
I2 GPO1 PWM1 PW2 PW1 I1 I1
GPO2
Figure 7-5. Driving Cross Coupled Coils The vector (I1,I2) of the currents through the coils in the cross coupled system is determined by the pulse widths (PW1, PW2). It also determines the elevation angle of the instrument.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 85
NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
7.7.2 H-Bridge Driver Special power drivers in the H-bridge must be used to drive the system with coils, because high voltages at the driver outputs due to switching the coils would damage the circuits if the drivers are not protected against this.
PVDD
AGREEMENT
POUT
L
R
POUT
PWM
GPO
PVSS
Figure 7-6. H-Bridge Driver Circuit
NON-DISCLOSURE
In order to avoid large switching currents through the N- and PMOS driver transistors both devices will not be active at the same time. On the other hand the switching delay between NMOS and PMOS transistor must be short, because the driver has to supply the coil circuit with a continuous current during the commutation. There would be diode currents into the bulk due to voltages below PVSS or greater then PVDD on the driver outputs if the commutation time is not short enough. Low voltage drops on the driver transistors are also necessary to avoid these diode currents.
General Release Specification 86 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F (Power Drivers)
7.7.3 Power Driver Circuit
PVDD
1 PMOS
POUT 2 NMOS
3 VIN
PVSS
Figure 7-7. Power Driver Circuit A high to low transition at the input VIN causes a low to high transition at the gate of the PMOS transistor. The NOR-gate 3 blocks the transition at VIN as long as the inverter 1 in the figure produces a low level. The result is that the PMOS and the NMOS devices are not active at the same time. An unsymmetrical sizing of the inverter 1 causes a fast propagation of the required low level to unblock the NOR-gate. This results in a short switching delay. The inverter 2 in the figure realizes a fast low to high transition at the output POUT.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 87
NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
7.7.4 Short Circuit Detection The drivers contain a short circuit detection mechanism. The pin value of a single power driver output is compared with the set level of the actual power driver. A difference between both levels indicates a short circuit case at the actual power driver. The difference is stored as a logic `1' in the corresponding bit of the mismatch registers of port E or port F. They can be polled by software. In the short circuit case precautions like shutting down the failed power driver can be taken.
AGREEMENT
PWEN PWM SOUT POWER DRIVER POUT
DB
D DR
Q
DRR
MRR
VDD Q MR R C MISL D Q HFF C D
EXOR
NON-DISCLOSURE
C
MRW SYN
Figure 7-8. Short Circuit Detection Circuitry Figure 7-8 shows the circuitry for a single power driver port bit. Each output bit of ports E and F can either be controlled directly by the data register or it is linked to the PWM function. The PWEN signal which corresponds to the appropriate bit in the PWEN register determines the functionality which will appear on the output.
General Release Specification 88 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F (Power Drivers)
7.7.5 Port E and Port F Mismatch Registers
$0041 Read:
Bit 7 bit 7
6 bit 6 0
5 bit 5 0
4 bit 4 0
3 bit 3 0
2 bit 2 0
1 bit 1 0
Bit 0 bit 0 0
Write: Reset: 0
Figure 7-9. Port E Mismatch Register (PEMISM) Bit 7-0 -- Port E short circuit indication The bits 7-0 indicate a short circuit on the port E. Each bit is cleared by writing a `1' to it. 1 = Short circuit at the corresponding port E pin 0 = No short circuit at the corresponding port E pin
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 89
NON-DISCLOSURE
AGREEMENT
The actual output level POUT of a single power driver is compared with the set output level SOUT via the EXOR gate in the circuitry. The buffer C provides `low' if the `high' set output is significantly lower than PVDD or it provides a `high' if the `low' set output is significantly higher than PVSS. The comparison result is latched with the appropriate signal SYN which runs at bus frequency. The timing of the signal SYN depends on the amount of microshifts for the actual PWM channel. The SYN signal occurs 1/4 of a bus cycle later than the start of the PWM period. This ensures the PWM signal being stable on the output POUT. A mismatch between the levels SOUT and POUT which indicates a short circuit on the output results in a `high' signal latched by the HFF. This latched mismatch signal MISL is now stored in the corresponding bit MR of the mismatch register. The mismatch register of port E or port F can be polled in a proper time period like an interrupt flag register. A read `high' on the mismatch register bit has to be handled like an interrupt flag. It will be cleared by writing a logic `1' back to this register.
REQUIRED
Input/Output Ports REQUIRED
$0043 Read: Write: Reset:
Bit 7 0
6 0
5 0
4 0
3 bit 3
2 bit 2 0
1 bit 1 0
Bit 0 bit 0 0
0
0
0
0
0
Figure 7-10. Port F Mismatch Register (PFMISM) Bit 3-0 -- Port F short circuit indication
AGREEMENT
The bits 3-0 indicate a short circuit on the port F. Each bit is cleared by writing a `1' to it. 1 = Short circuit at the corresponding port F pin 0 = No short circuit at the corresponding port F pin
7.7.6 Driver States A single H-bridge realizes a current through the coil in both directions. Three states are necessary to realize the required H-bridge operations for the 360 aircore instruments. * Forward State - M1, M2 off; M0, M3 on Backward State - M0, M3 off; M1, M2 on Off State - M0, M2 off; M1, M3 on
NON-DISCLOSURE
* *
The Mx are the driver transistors which form the H-bridge. The following circuits show how the bridge can operate in the different states. The driver transistors are drawn as switches for simplification.
General Release Specification 90 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F (Power Drivers)
FORWARD STATE I M1 M3 M1
OFF STATE
M3
L
P LEFT
R
P RIGHT P LEFT
L
R
P
M0
M2
M0
M2
PWM
GPO
PWM
GPO
BACKWARD STATE I
OFF STATE
M1
M3
M1
M3
L
P LEFT
R
P RIGHT P LEFT
L
R
P
M0
M2
M0
M2
GPO
PWM
GPO
PWM
Figure 7-11. H-Bridge States In each state the output driver GPO must hold the output Pleft or Pright (left or right port line) at voltage PVDD-Vdrop while the PWM driver switches the opposite part of the H-bridge to ground. The PWM driver switches between forward state and off state or backward state and off state. The average current I is determined by the pulse width ratio at the PWM driver. Current direction is changed by switching between forward and backward state. The output and the PWM functionality has also been changed between the two port lines when switching current direction.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 91
NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output Ports REQUIRED
7.7.7 Port E and Port F Configurations Figure 7-12 shows a port E configuration which controls two 360 aircore instruments or stepper motors. One power driver block controls a single large angle instrument (360). This configuration ensures a minimum voltage drop mismatch between the two H-bridges of the block.
NOTE:
AGREEMENT
One should not control a single instrument with H-bridges from different power driver blocks. The minimum voltage drop mismatch is only ensured within a single block.
LEFT PWM0 RIGHT LEFT PWM1 RIGHT LEFT
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7
NON-DISCLOSURE
PWM2 RIGHT LEFT PWM3 RIGHT
Figure 7-12. Port E Configuration for two 360 instruments
General Release Specification 92 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F (Power Drivers)
PVDD
PWM4 PWM5 PWM6 PWM7
PF0 PF1 PF2 PF3
Figure 7-13. Port F Configuration for four 90 instruments (version 1)
PVDD
PWM4 PWM5 PWM6 PWM7
PF0 PF1 PF2 PF3 PVSS
Figure 7-14. Port F Configuration for four 90 instruments (version 2) Figure 7-13 and Figure 7-14 show two port F configuration with four 90 small angle instruments which are controlled by the PWM. The small angle instrument does not need a switching between two quadrants. It can be controlled by a single power driver and its PWM.
NOTE:
If port E (PWM channels 0 to 3) is used to control small angle instruments, the SIGN bit in the PWM control register may not be changed during the operation with 90 instruments. This would exchange the functionality of PWM and GPO (general purpose output) between the left and the right port bit.
General Release Specification Input/Output Ports 93
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
NON-DISCLOSURE
AGREEMENT
PVSS
REQUIRED
Input/Output Ports REQUIRED
7.7.8 H-Bridge Control with the PWM The current in the PWM can be adjusted in the range of -Imax x 256/256 and + Imax x 255/256. The current is a linear function of the 8+1bit 2's complement value in the data register of the PWM channel. The SIGN bit controls the current direction within the H-bridge. This will be done by exchanging the PWM and GPO functionality and inverting the PWM signal in the H-bridge when switching the SIGN-bit.
AGREEMENT
POL = 1 SIGN = 0 I M1 M3 M1 SIGN = 1 I M3
L
LEFT
R
P RIGHT P LEFT
L
R
P RIGHT
M0
M2
M0
M2
PWM
GPO = HIGH
GPO = HIGH
PWM
NON-DISCLOSURE
Figure 7-15. H-Bridge Control with PWM The following 3 bit PWM example in Figure 7-16 shows the correspondence between the 2's complement values in the data register and the required PWM signal in the H-bridge.
General Release Specification 94 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Input/Output Ports Port E and Port F During WAIT Mode
7 : 2 1 0 -1 -2 :
0 111
0 010 0 001 0 000 1 111 1 110
SIGN
Figure 7-16. Correspondence between Data and PWM Values Figure 7-16 shows that the PWM signal has to be inverted for the negative values in order to obtain the correct H-bridge signal which is drawn in Figure 7-16. (Compare the periods for the values -1 and 7).
In WAIT mode a mask option defines if port E and port F will be forced to output `low' or if port E and port F continue normal operation.
7.9 Input/Output Programming
Bidirectional port lines may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logical zero.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Input/Output Ports
General Release Specification 95
NON-DISCLOSURE
7.8 Port E and Port F During WAIT Mode
AGREEMENT
-8
1 000
REQUIRED
Input/Output Ports REQUIRED
At power-on or reset, all DDRs are cleared, which configure all port pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin.
Table 7-1. I/O Pin Functions
R/W DDR
0 1 0 1
I/O Pin Function
The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read.
AGREEMENT
0 0 1 1
R/W is an internal signal.
Data Direction Register Bit
NON-DISCLOSURE
Internal HC05 Connections
Latched Output Data Bit Input Reg Bit Input I/O
Output
I/O Pin
Figure 7-17. Port I/O Circuitry
NOTE:
If the I/O pin is an input and a read-modify (RMW) instruction is executed, the I/O pin will be read into the HC05 CPU and the computed result will then be written to the data latch.
General Release Specification 96 Input/Output Ports
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Core Timer Contents
General Release Specification -- MC68HC(7)05H12
Section 8. Core Timer
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 Core Timer Status and Control Register (CTSCR) . . . . . . . 99 8.3.2 Computer Operating Properly (COP) Watchdog Reset. . . 101 8.3.3 Core Timer Counter Register (CTCR). . . . . . . . . . . . . . . . 101 8.4 Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.2 Introduction
The core timer for this device is a 15-stage multi-functional ripple counter. The features include timer over flow, power-on reset (POR), real time interrupt (RTI), and COP watchdog timer.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Core Timer
General Release Specification 97
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED
INTERNAL BUS 8 8 8 Internal Processor Clock COP Clear $9 CTCR Timer Counter Register (TCR) TCR fop /210 fop fop /22
/4
AGREEMENT
7-bit counter
POR TCBP RTI Select Circuit
Overflow Detect Circuit
$08 CTCSR Timer Control/Status Register TCSR TOF RTIF TOFE RTIE RTOF RRTIF RT1 RT0
NON-DISCLOSURE
COP Watchdog Interrupt Circuit Timer (/8)
To Interrupt Logic
To Reset Logic
Figure 8-1. Core Timer Block Diagram As seen in Figure 8-1, the Timer is driven by the output of the clock select circuit followed by a fixed divide by four prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the timer counter register (TCR) at address $09. A timer overflow function is implemented on the
General Release Specification 98 Core Timer
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Core Timer Registers
last stage of this counter, giving a possible interrupt at the rate of fop/1024. Two additional stages produce the POR function at fop/4064. The timer counter bypass circuitry (available only in Test Mode) is at this point in the timer chain. This circuit is followed by two more stages, with the resulting clock (fop/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits, and the RTI and TOF enable bits and flags are located in the timer control and status register at location $08.
8.3 Registers
8.3.1 Core Timer Status and Control Register (CTSCR) The CTSCR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTSCR when coming out of reset.
Read: Write: Reset:
TOF
RTIF TOFE RTIE
0 RTOF
0 RT! RRTIF 0 1 1 RT0
0
0
0
0
0
Figure 8-2. Core Timer Status and Control Register (CTSCR) TOF - Timer Over Flow TOF is a read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if TOFE is set. Reset clears TOF. RTIF - Real Time Interrupt Flag The real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. The clock frequency that drives the RTI circuit is fop/213 (or fop/8192) with three additional divider stages giving a maximum
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Core Timer General Release Specification 99
NON-DISCLOSURE
$0008
Bit 7
6
5
4
3
2
1
Bit 0
AGREEMENT
REQUIRED
Core Timer REQUIRED
interrupt period of about 250ms seconds at a crystal frequency of 1 MHz. RTIF is a read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. A CPU interrupt request will be generated if RTIE is set. Reset clears RTIF. TOFE - Timer Over Flow Enable When this bit is set, a CPU interrupt request is generated when the TOF bit is set. Reset clears this bit. RTIE - Real Time Interrupt Enable
AGREEMENT
When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. RTOF -- Reset Timer Overflow Flag This bit reads always as `0'. Writing a `1' to this bit clears the timer overflow flag (TOF). Writing a zero to this bit has no effect. RRTIF -- Reset Real Time Interrupt Flag This bit reads always a `0'. Writing a `1' to this bit clears the real time interrupt flag (RTIF). Writing a zero to this bit has no effect. RT1, RT0 - Real Time Interrupt Rate Select
NON-DISCLOSURE
These two bits select one of four taps from the real time interrupt circuit. Figure 8-1shows the available interrupt rates with several fop values. Reset sets these RT0 and RT1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps.
Table 8-1. RTI Rates
RTI Rates at Bus Frequency fOP specified: RT1:RT0
00
500 kHz
32.768ms
1.000 MHz
16.384ms
2.000 MHz
8.192ms
2.4576 MHz
6.667ms
RATIO
214/fop
General Release Specification 100 Core Timer
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Core Timer Registers
Table 8-1. RTI Rates
RTI Rates at Bus Frequency fOP specified: RT1:RT0
01 10 11
500 kHz
65.536ms 131.072ms 262.144ms
1.000 MHz
32.768ms 65.536ms 131.072ms
2.000 MHz
16.384ms 32.768ms 65.536ms
2.4576 MHz
13.333ms 26.667ms 53.333ms
RATIO
215/fop 216/fop 217/fop
8.3.2 Computer Operating Properly (COP) Watchdog Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-2. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP time-out is done by writing a `0' to bit 0 of address $3FF0. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared.
Table 8-2. Minimum COP Reset Times
Minimum COP Reset Bus Frequency at fOP specified:
7*214/fop 7*215/fop 7*216/fop 7*217/fop
00 01 10 11
229.376ms 458.752ms 917.504ms 1835.000ms
114.689ms 229.376ms 458.752ms 917.504ms
57.344ms 114.689ms 229.376ms 458.752ms
46.666ms 93.333ms 186.666ms 373.333ms
8.3.3 Core Timer Counter Register (CTCR) The timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fop divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Core Timer
General Release Specification 101
NON-DISCLOSURE
RT1:RT0
500 kHz
1.000 MHz
2.000 MHz
2.4576 MHz
RATIO
AGREEMENT
REQUIRED
Core Timer REQUIRED
$0009 Read: Write: Reset:
Bit 7 bit 7
6 bit 6
5 bit 5
4 bit 4
3 bit 3
2 bit 2
1 bit 1
Bit 0 bit 0
0
0
0
0
0
0
0
0
Figure 8-3. Core Timer Counter Register (CTCR) The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted anytime during operation (other than POR), the counter chain will be cleared.
AGREEMENT
8.4 Core Timer During WAIT
The CPU clock halts during the WAIT mode, but the core timer remains active. If the CTIMER interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
NON-DISCLOSURE
General Release Specification 102 Core Timer
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 9. 16-Bit Timers
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.2 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.3 Output Compare Register 1 . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.4 Output Compare Register 2 . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.6 Input Capture Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.7 Input Capture Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.8 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.9 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.10 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.4 Timer During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.2 Introduction
The MC68HC(7)05H12 has two 16-bit timers (Timer1 and Timer2) each with two channels. The output compare function in Timer2 has no external outputs, so it is used for generating precision time intervals and interrupts only. Write access to the corresponding output level register bits OLVL3 and OLVL4 has no effect. Apart from this difference in the external connections, the internal operation of both is identical (each timer having its own set of registers, see Section 2.3 Registers), therefore only a complete description of Timer1 is given. The timer consists of a 16-bit, free running counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers General Release Specification 103
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AGREEMENT
REQUIRED
16-Bit Timers REQUIRED
microseconds to many seconds. Refer to Figure 9-1 for a timer block diagram. Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed.
AGREEMENT
NOTE:
The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur.
Internal Bus Internal Processor 8-Bit Clock Buffer High Low Byte Byte /4 16-Bit Free $28 Running $29 Counter Counter Alternate Register $2A $2B Low Byte
High Byte
High Byte
Low Byte
High Byte
Low Byte $20 $21
High Byte
Low Byte $24 $25
$22 $23 Output Compare Register 2 $26 $27
Input Capture 1 Register Edge Input (TCAP2) Edge Detect Circuit Edge Input (TCAP1)
Input Capture 2 Register
Output Compare Register 1 Output Level (TCOMP0) DQ CLK
NON-DISCLOSURE
Edge Detect Circuit
Overflow Detect Circuit
Output Compare Circuit 2
Output Compare Circuit 1
C Output Level (TCOMP1) DQ CLK
Timer Status Reg.
ICI1E IC1F IC2F OC1F TOF OC2F
ICI2E OCI1E TOIE IEDG1 IEDG2 OLVL1 TCR1($2C) RESET OCI2E OLVL2 TCR2($2D)
C
Interrupt Circuit
Figure 9-1. Timer Block Diagram (Timer1)
General Release Specification 104 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
16-Bit Timers Registers
9.3 Registers
Addr
$0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E
Register Name
Timer1 Capture 1 High Timer1 Capture 1 Low Timer1 Compare 1 High Timer1 Compare 1 Low Timer1 Capture 2 High Timer1 Capture 2 Low Timer1 Compare 2 Low Timer1 Counter High Timer1 Counter Low Timer1 Alternate Counter High Timer1 Alternate Counter Low Timer1 Control 1 Timer1 Control 2 Timer1 Status Timer1 Compare 2 High
Figure 9-2. 16-Bit Timer Register Addresses (Timer1)
9.3.1 Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $28-$29 (counter register) or $2A-$2B (counter alternate register). A read from only the least significant byte (LSB) of the freerunning counter ($29, $2B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte ($28, $2A), the LSB ($29, $2B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers
General Release Specification 105
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timers REQUIRED
register LSB ($29 or $2B) and thus completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: a read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF.
AGREEMENT
9.3.2 Output Compare Registers There are two output compare registers: output compare register 1 and output compare register 2. Output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations.
NON-DISCLOSURE
9.3.3 Output Compare Register 1 The 16-bit output compare register 1 is made up of two 8-bit registers at locations $22 (MSB) and $23 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare flag OC1F (bit 5 of the timer status register ($2E)) is set and the corresponding output level OLVL1 bit is clocked to TCMP1 output. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCI1E) is set. After a processor write cycle to the output compare register 1 containing the MSB ($22), the output compare function is inhibited until the LSB
General Release Specification 106 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
16-Bit Timers Registers
($23) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($23) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register 1 without affecting the other byte. The output level (OLVL1) bit is clocked to the output level register regardless of whether the output compare flag (OC1F) is set or clear. Because the output compare flag OC1F and the output compare register 1 are undetermined at power-on and are not affected by external reset, care must be exercised when initializing the output compare function. The following procedure is recommended Write the high byte to the compare register 1 to inhibit further compares until the low byte is written. Reading the status register arms the OC1F if it is already set. Write the output compare register 1 low byte to enable the output compare 1 function with the flag clear. The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read and the write to the corresponding output compare register.
9.3.4 Output Compare Register 2 The 16-bit output compare register 2 is made up of two 8-bit registers at locations $26 (MSB) and $27 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare flag OC2F (bit 1 of the timer status register ($2E)) is set and the corresponding output level OLVL2 bit is clocked to TCMP2 output.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers
General Release Specification 107
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timers REQUIRED
The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCI2E) is set. After a processor write cycle to the output compare register 2 containing the MSB ($26), the output compare function is inhibited until the LSB ($27) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($27) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register 2 without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register regardless of whether the output compare flag (OC2F) is set or clear. Because the output compare flag OC2F and the output compare register 2 are undetermined at power-on, and are not affected by external reset care must be exercised when initializing the output compare function. A procedure as recommended for compare register 1 should be followed.
NON-DISCLOSURE
AGREEMENT
9.3.5 Input Capture Registers There are two identical input capture registers: input capture register 1 and input capture register 2. The two following sections describe these two registers.
9.3.6 Input Capture Register 1 Two 8-bit registers, which make up the 16-bit input capture register 1, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the TCAP1 pin. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG1). Reset does not affect the contents of the input capture register.
General Release Specification 108 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
16-Bit Timers Registers
IEDG1 -- Capture on Negative/Positive Edge 1 = Capture on positive edge 0 = Capture on negative edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI1E is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC1F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register most significant byte ($20), the counter transfer is inhibited until the least significant byte ($21) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($21) does not inhibit the freerunning counter transfer since they occur on opposite edges of the internal bus clock.
9.3.7 Input Capture Register 2 Two 8-bit registers, which make up the 16-bit input capture register 2, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the TCAP2 pin. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG2). Reset does not affect the contents of the input capture register.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers
General Release Specification 109
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timers REQUIRED
IEDG2 -- Capture on Negative/Positive Edge 1 = Capture on positive edge 0 = Capture on negative edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI2E is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC2F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register most significant byte ($24), the counter transfer is inhibited until the least significant byte ($25) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($25) does not inhibit the freerunning counter transfer since they occur on opposite edges of the internal bus clock.
NON-DISCLOSURE
AGREEMENT
9.3.8 Timer Control Register 1
$002C Read:
Bit 7 ICI1E
6 ICI2E 0
5 OCI1E 0
4 TOIE 0
3 CO1E 0
2 IEDG1 U
1 IEDG2 U
Bit 0 OLVL1 0
Write: Reset: 0
Figure 9-3. Timer Control Register 1 (TCR1)
General Release Specification 110 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
16-Bit Timers Registers
ICI1E -- Input Capture 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled ICI2E -- Input Capture 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCI1E -- Output Compare 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE -- Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled CO1E -- Timer Compare 1 Output Enable Reset clears this bit. 1 = Output of timer compare 1is enabled 0 = Output of timer compare 1is disabled, i.e. held low IEDG1 -- Input Edge Value of input edge determines which level transition on TCAP1 pin will trigger free-running counter transfer to the input capture register 1. 1 = Positive edge 0 = Negative edge IEDG2 -- Input Edge Value of input edge determines which level transition on TCAP2 pin will trigger free-running counter transfer to the input capture register 2. 1 = Positive edge 0 = Negative edge OLVL1 -- Output Level 1 Value of output level is clocked into output level register by the next successful output compare 1, and will appear on the TCMP1 pins. 1 = High output 0 = Low output
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers General Release Specification 111
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timers REQUIRED
9.3.9 Timer Control Register 2
$002D Read: Write: Reset:
Bit 7 0
6 0
5 OCI2E
4 0
3 CO2E
2 0
1 0
Bit 0 OLVL2
U
U
0
0
U
0
0
U
Figure 9-4. Timer Control Register 2 (TCR2)
AGREEMENT
OCI2E -- Output Compare 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled CO2E -- Timer Compare 2 Output Enable Reset clears this bit. 1 = Output of timer compare 2 is enabled 0 = Output of timer compare 2 is disabled, i.e. held low OLVL2 -- Output Level 2 Value of output level is clocked into output level register by the next successful output compare 2, and will appear on the TCMP2 pin. 1 = High output 0 = Low output Bits 1,2,4,6 & 7 of TRC2 are no used and always read zero.
NON-DISCLOSURE
NOTE:
Only TCMP1 and TCMP2 of Timer 1 are available at port C, Timer 2 has no TCMP pins.
General Release Specification 112 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
16-Bit Timers Registers
9.3.10 Timer Status Register The timer status register is a read-only register containing timer status flags.
$002E Read: Write: Reset: U U U U 1 1 U 0 Bit 7 IC1F 6 IC2F 5 OC1F 4 TOF 3 TCAP1 2 TCAP2 1 OC2F Bit 0 0
IC1F -- Input Capture 1 Flag 1 = Flag set when selected polarity edge is sensed by input capture 1 edge detector 0 = Flag cleared when TSR and input capture 1 register's low byte is accessed IC2F -- Input Capture 2 Flag 1 = Flag set when selected polarity edge is sensed by input capture 2 edge detector 0 = Flag cleared when TSR and input capture 2 register's low byte is accessed OC1F -- Output Compare 1 Flag 1 = Flag set when output compare register 1 contents match the free-running counter contents 0 = Flag cleared when TSR and output compare register 1 low byte are accessed TOF -- Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register are accessed TCAP1 -- Timer Capture 1 This bit reflects the current state of the timer capture 1 input. TCAP2 -- Timer Capture 2 This bit reflects the current state of the timer capture 2 input.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA 16-Bit Timers
General Release Specification 113
NON-DISCLOSURE
AGREEMENT
Figure 9-5. Timer Status Register (TSR)
REQUIRED
16-Bit Timers REQUIRED
OC2F -- Output Compare 2 Flag 1 = Flag set when output compare register 2 contents match the free-running counter contents 0 = Flag cleared when TSR and output compare register 2 low byte are accessed Accessing the timer status registers satisfies the first condition required to clear status bits. The remaining step is to access the registers corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set, and 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag The counter alternate register contains the same value as the freerunning counter; therefore this alternate register can be read at any time without affecting the timer overflow flag in the timer status register.
NON-DISCLOSURE
AGREEMENT
9.4 Timer During WAIT Mode
The CPU clock halts during the WAIT mode but the timer keeps on running. If a reset is used to exit the WAIT mode the counters are forced to $FFFC. If interrupts are enabled a timer interrupt will cause the processor to exit WAIT mode.
General Release Specification 114 16-Bit Timers
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 10. Serial Peripheral Interface (SPI)
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10.3 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . 117 10.3.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4 SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.5.1 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . 121 10.5.2 SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.3 SPI Data I/O Register (SPDAT) . . . . . . . . . . . . . . . . . . . . 124 10.6 SPI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.2 Introduction
The SPI is a synchronous interface which allows several SPI microcontrollers or SPI-type peripherals to be interconnected. In a serial peripheral interface, separate wires (signals) are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. The MC68HC(7)05H12 SPI system may be configured either as a master or as a slave.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification 115
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Peripheral Interface (SPI) REQUIRED
Features include: * * * * * * Full-duplex, 3-wire synchronous transfers Master or slave operation 2.50 MHz (maximum) master bit frequency 5.0 MHz (maximum) slave bit frequency Four programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Write collision flag protection Master-master mode fault protection Easy interface to simple expansion parts (PLLs, D/As, latches, display drivers, etc.) Very low clock rates by reuse of the SCI prescalers.
AGREEMENT
* * * * *
10.3 SPI Signal Description
Three I/O pins located at port B are associated with the SPI data transfers. They are the serial clock (SCK), the master in/slave out (MISO) data line, the master out/slave in (MOSI) data line. When the SPI system is not utilized (SPE bit cleared in the serial peripheral control register), the three pins (MISO, MOSI, SCK) are configured as generalpurpose I/O pins. The three SPI signals are discussed in the following paragraphs for both master mode and slave mode of operation.
NON-DISCLOSURE
NOTE:
The SPI subsystem works as master and does not have a slave select input line (SS).
10.3.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected.
General Release Specification 116 Serial Peripheral Interface (SPI) MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Peripheral Interface (SPI) SPI Signal Description
10.3.2 Master Out Slave In (MOSI) The MOSI line is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction with the most significant bit sent first.
10.3.3 Serial Clock (SCK) The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown in Figure 10-1, four different timing relationships may be selected by control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK), in order for the slave device to latch the data. Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification 117
NON-DISCLOSURE
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REQUIRED
Serial Peripheral Interface (SPI) REQUIRED
SCK (CPOL = 0, CPHA = 0)
SCK (CPOL = 0, CPHA = 1)
AGREEMENT
SCK (CPOL = 1, CPHA = 0)
SCK (CPOL = 1, CPHA = 1) MISO / MOSI MSB 6 5 4 3 2 1 LSB
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
NON-DISCLOSURE
General Release Specification 118 Serial Peripheral Interface (SPI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Peripheral Interface (SPI) SPI Functional Description
10.4 SPI Functional Description
INTERNAL MCU CLOCK
SCI CLOCK S M MSB LSB M S PB5/ MISO
DIVIDER READ DATA BUFF
CLOCK SELECT SPR1 SPR0 SPI CLOCK (MASTER) CLOCK LOGIC S M
PB7/ SCK
MSTR SPI CONTROL WCOL MODF SPE MSTR CPHA CPOL SPR1 SPR0
SPIF
SPIE SPE DOD
SPI STATUS REGISTER
SPI CONTROL REGISTER
SPI INTERRUPT REQUEST
INTERNAL DATA BUS
Figure 10-2. Serial Peripheral Block Diagram Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave device via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized to the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmitter-empty and receiver-full
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification 119
NON-DISCLOSURE
AGREEMENT
/2 /4 /16 /32
PIN CONTROL LOGIC
8-BIT SHIFT REG
PB6/ MOSI
REQUIRED
Serial Peripheral Interface (SPI) REQUIRED
status bits. A single status bit (SPIF) is used to signify that the I/O operation has been completed. The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer is not interrupted, and the write will be unsuccessful. This condition will cause the write collision status bit (WCOL) in the SPSR to be set. After a data byte is shifted, the SPIF flag in the SPSR is set. In master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register. Then eight clocks are generated to shift the eight bits of data, after which SCK goes idle again. In slave mode, the slave start logic receives a clock input at the SCK pin. Thus, the slave is synchronized to the master. Data from the master is received serially via the slave MOSI line and is loaded into the 8-bit shift register. The data is then transferred, in parallel, from the 8-bit shift register to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line. Figure 10-3 illustrates the MOSI, MISO and SCK master-slave interconnections.
NON-DISCLOSURE
AGREEMENT
MASTER 8-BIT SHIFT REGISTER MISO MOSI MISO MOSI
SLAVE 8-BIT SHIFT REGISTER
SPI CLOCK GENERATOR
SCK
SCK
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
General Release Specification 120 Serial Peripheral Interface (SPI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Peripheral Interface (SPI) Registers
10.5 Registers
There are three registers in the serial peripheral interface which provide control, status and data storage functions. These registers are called the serial peripheral control register (SPCR), the serial peripheral status register (SPSR) and the serial peripheral data I/O register (SPDAT).
10.5.1 SPI Control Register (SPCR)
$0044 Read:
Bit 7 SPIE
6 SPE 0
5 DOD 0
4 MSTR 0
3 CPOL 0
2 CPHA 1
1 SPR1 U
Bit 0 SPR0 U
Write: Reset: 0
Figure 10-4. SPI Control Register (SPCR) SPIE -- SPI Interrupt Enable When this bit is set to one, a hardware interrupt sequence is requested each time the SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the CC Register is set. 1 = SPI interrupts enabled 0 = SPI interrupts disabled SPE -- SPI System Enable 1 = SPI system on 0 = SPI system off DOD -- Direction of Data Flow (in or out of the Serial Shift Register) 1 = data is transferred LSB first 0 = data is transferred MSB first MSTR -- Master/Slave Mode Select 1 = Master mode 0 = Slave mode
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification 121
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REQUIRED
Serial Peripheral Interface (SPI) REQUIRED
CPOL -- Clock Polarity When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. See Figure 10-1. CPHA -- Clock Phase
AGREEMENT
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of simply as inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. Refer to Figure 10-1. SPR1, SPR0 -- SPI Clock Rate Selects If the device is a master, the two serial peripheral rate bits select one of four division ratios of the input-clock to be used as SCK (see Table 10-1). These bits have no effect in slave mode.
NON-DISCLOSURE
Table 10-1. SPI Clock Rate Selection
SPR1
0 0 1 1
SPR0
0 1 0 1
Input clock divided by PRS0
2 4 16 32
Bit 6 (SPP = SPI Prescaler) of the SCI baud rate register, Section 11.8.5 Baud Rate Register (BAUD), determines the input clock of the SPI module. SPP -- SPI Prescaler 1 = SCI receiver clock connected to the SPI clock input 0 = bus clock connected to the SPI clock input
NOTE:
If SPP is set, the SPI clock rate is dependent on the SCI clock rate. The SPI clock rate is given by E: PRS1: PRS2: PRS0. PRS1 and PRS2 are
General Release Specification 122 Serial Peripheral Interface (SPI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Peripheral Interface (SPI) Registers
the SCI prescaler factors given in Table 11-1 and Table 11-2. PRS0 is the SPI prescaler factor given in Table 10-1.
10.5.2 SPI Status Register (SPSR)
$0045 Read: Write: Reset:
Bit 7 SPIF
6 WCOL
5 0
4 0
3 0
2 0
1 0
Bit 0 0
0
0
0
0
0
0
0
0
Figure 10-5. SPI Status Register (SPSR) SPIF -- SPI Interrupt Request Flag The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPSR register (with SPIF set) followed by reading from or writing to the SPI Data Register (SPDAT). WCOL -- Write Collision The write collision bit is used to indicate that a serial transfer was in progress when the MCU tried to write new data into the SPDAT data register. The MCU write is disabled to avoid writing over the data being transmitted. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. This flag is automatically cleared by a read of the SPSR (with WCOL set) followed by an access (read or write) to the SPDAT register.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification 123
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Peripheral Interface (SPI) REQUIRED
10.5.3 SPI Data I/O Register (SPDAT)
$0046 Read: Write: Reset:
Bit 7 bit 7
6 bit 6
5 bit 5
4 bit 4
3 bit 3
2 bit 2
1 bit 1
Bit 0 bit 0
U
U
U
U
U
U
U
U
Figure 10-6. SPI Data I/O Register (SPDAT)
AGREEMENT
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission.
NON-DISCLOSURE
10.6 SPI During WAIT Mode
When the MCU enters wait mode, the CPU clock is halted. All CPU action is suspended; however, the SPI system remains active. In fact an interrupt from the SPI causes the processor to exit the wait mode.
General Release Specification 124 Serial Peripheral Interface (SPI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 11. Serial Communications Interface (SCI)
11.1 Contents
11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.4 Receiver Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4.1 Idle Line Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.2 Address Mark Wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.5 11.6 11.7 Receive Data (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Transmit Data (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
11.9
SCI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.2 Introduction
The SCI is a full-duplex UART-type asynchronous system, using standard non return-to-zero (NRZ) format (one start bit, eight or nine data bits, and a stop bit). An on-chip baud-rate generator derives standard baud-rate frequencies from the MCU oscillator. Both the transmitter and the receiver are double buffered; thus, back-to-back characters can be handled easily, even if the central processing unit (CPU) is delayed in responding to the completion of an individual character. The SCI transmitter and receiver are functionally independent but use the same format and baud rate.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI) General Release Specification 125
NON-DISCLOSURE
11.8 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8.1 Serial Communications Data Register (SCDAT). . . . . . . . 135 11.8.2 Serial Communications Control Register 1 (SCCR1) . . . . 136 11.8.3 Serial Communications Control Register 2 (SCCR2) . . . . 137 11.8.4 Serial Communications Status Register (SCSR) . . . . . . . 138 11.8.5 Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . 140
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED
SCI Two-wire System Features: * * * * * Standard NRZ (mark/space) format. Advanced error detection method includes noise detection for noise duration of up to 1/16th bit time. Full-duplex operation. Software programmable for one of 32 different baud rates. Software selectable word length (eight or nine bit words). Separate transmitter and receiver enable bits. Capable of being interrupt driven. Four separate enable bits available for interrupt control.
AGREEMENT
* * *
SCI Receiver Features: * * * * * * Receiver wake-up function (idle line or address bit). Idle line detect. Framing error detect. Noise detect. Overrun detect. Receiver data register full flag.
NON-DISCLOSURE
SCI Transmitter Features: * * * Transmit data register empty flag. Transmit complete flag. Send break.
A block diagram of the SCI is shown in Figure 11-1. The user has option bits in serial communication control register 1 (SCCR1) to select the `wake-up' method (WAKE bit) and data word length (M bit) of the SCI. Serial communications control register 2 (SCCR2) provides control bits which individually enable/disable the transmitter or receiver (TE and RE, respectively), enable system interrupts (TIE, TCIE, RIE, ILIE) and provide the wake-up enable bit (RWU) and the send break code bit
General Release Specification 126 Serial Communications Interface (SCI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Introduction
(SBK). Control bits in the baud rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and receiver.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 127
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED
SCI INTERRUPT
INTERNAL BUS
$47
TRANSMIT DATA REGISTER SCCR2 $49 TIE TCIE TRANSMIT DATA SHIFT REGISTER RIE ILIE TE RE SCSR FE NF OR DLE RDRF TC TDRE $4A TDO 2 WAKE-UP UNIT SBK TE 7 RECEIVE CONTROL INTERNAL PROCESSOR DATA SBK RWU
RECEIVE DATA $47 REGISTER
(SEE NOTE)
AGREEMENT
(SEE NOTE)
RECEIVE DATA SHIFT REGISTER
RDI
NON-DISCLOSURE
TRANSMIT CONTROL
FLAG CONTROL
RATE GENERATOR
$4B TCLR
SPP
SCP1 SCP0 RCKB SCR2 SCR1 SCR0 BAUD
$48
R8
T8
0
M
WAKE
0
0
0
SCCR1
Figure 11-1. Serial Communications Interface Block Diagram
General Release Specification 128 Serial Communications Interface (SCI) MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Introduction
NOTE:
The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal. It is the transmit data register when written and the receive data register when read.
Data transmission is initiated by a write to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and may generate an interrupt if the transmit interrupt is enabled. The transfer of data to the transmit data shift register is synchronized with the bit rate clock. All data is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or break is to be sent), and an interrupt may be generated if the transmit complete interrupt is enabled. If the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled in the middle of a transmission, that character will be completed before the transmitter gives up control of the TDO pin. When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR, which can cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception errors occurred. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message, or to resynchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 129
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED 11.3 Data Format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-tozero (NRZ) data format shown in Figure 11-2 is used and must meet the following 5 criteria: 1. The idle line is brought to a logic one state prior to transmission/reception of a character. 2. A start bit (logic zero) is used to indicate the start of a frame. 3. The data is transmitted and received least significant bit first. 4. A stop bit (logic one) is used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. 5. A break is defined as the transmission or reception of a low (logic zero) for at least one complete frame time.
AGREEMENT
CONTROL BIT `M' SELECTS 8 OR 9 BIT DATA
{
NON-DISCLOSURE
IDLE LINE
0
1
2
3
4
5
6
7
8
0
START
STOP START
OPTIONAL
Figure 11-2. Data Format
11.4 Receiver Wake-up Operation
The receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. The wake-up function allows receivers not
General Release Specification 130 Serial Communications Interface (SCI) MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Receiver Wake-up Operation
addressed to remain in a dormant state for the remainder of the unwanted message. This eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance. The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally RWU is set by software and gets cleared automatically with hardware by one of the two methods described below.
11.4.1 Idle Line Wake-up In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems using this type of wake-up must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message.
11.4.2 Address Mark Wake-up In address mark wake-up, the most significant bit (MSB) in a character is used to indicate that the character is an address (1) or a data (0) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wake-up would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wakeup method.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 131
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED 11.5 Receive Data (RDI)
Receive data is the serial data that is applied through the input line and the serial communications interface to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate and this time is referred to as the RT clock. Once a valid start bit is detected the start bit, each data bit and the stop bit are sampled three times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start), as shown in Figure 113. The value of the bit is determined by voting logic which takes the value of the majority of the samples.
AGREEMENT
PREVIOUS BIT
PRESENT BIT
SAMPLES
NEXT BIT
RDI
V
V
V
16 R T
1 R T
8 R T
9 R T
10 R T
16 R T
1 R T
NON-DISCLOSURE
Figure 11-3. Sampling Technique Used On All Bits
11.6 Start Bit Detection
When the RDI input is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 11-4). If at least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A noise flag is set if all three verification samples do not detect a logic zero. A valid start bit could be assumed with a set noise flag present. If there has been a framing error without detection of a break (10 zeros for 8-bit format or 11 zeros for 9-bit format), the circuit continues to operate as if there actually was a stop bit and the start edge will be placed artificially. The last bit received in the data shift register is
General Release Specification 132 Serial Communications Interface (SCI) MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Start Bit Detection
inverted to a logic one, and the three logic one start qualifiers (shown in Figure 11-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 11-5); therefore, the start bit will be accepted no sooner than it is anticipated. If the receiver detects that a break produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before the start bit can be recognised (see Figure 11-6).
16X INTERNAL SAMPLING CLOCK
RT CLOCK EDGES (FOR ALL THREE EXAMPLES) IDLE RDI
1 R T
2 R T START
3 R T
4 R T
5 R T
1
1
1
1
1
1
1
1
1
1
0
0
0 START VERIFICATION NOISE
START QUALIFIERS IDLE RDI START
1
1
1 IDLE
1
1 NOISE
1
1
1
1
1
0
0
1
RDI
START
1
1
1
1
0
1
1
1
1
1
0
0
0
Figure 11-4. Examples of Start Bit Sampling Techniques
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 133
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED
DATA
EXPECTED STOP
ARTIFICIAL EDGE
RECEIVE DATA IN
START BIT DATA
DATA SAMPLES (A) CASE 1, RECEIVE LINE LOW DURING ARTIFICIAL EDGE
AGREEMENT
DATA
EXPECTED STOP
START EDGE
RECEIVE DATA IN
START BIT DATA
DATA SAMPLES
(B) CASE 2, RECEIVE LINE HIGH DURING EXPECTED START EDGE
Figure 11-5. SCI Artificial Start Following a Framing Error
NON-DISCLOSURE
EXPECTED STOP BREAK RECEIVE DATA IN
DETECTED A START EDGE START BIT
START QUALIFIERS DATA SAMPLES
START EDGE VERIFICATION SAMPLES
Figure 11-6. SCI Start Bit Following a Break
General Release Specification 134 Serial Communications Interface (SCI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Transmit Data (TDO)
11.7 Transmit Data (TDO)
Transmit data is the serial data from the internal data bus that is applied through the serial communications interface to the output line. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock.
11.8 Registers
Primarily the SCI system is configured and controlled by five registers BAUD, SCCR1, SCCR2, SCSR, and SCDAT.
11.8.1 Serial Communications Data Register (SCDAT)
$0047 Read:
Bit 7 bit 7
6 bit 6 U
5 bit 5 U
4 bit 4 U
3 bit 3 U
2 bit 2 U
1 bit 1 U
Bit 0 bit 0 U
Write: Reset: U
Figure 11-7. SCI Data Register (SCDAT) The SCI data register (SCDAT) shown in Figure 11-7 is actually two separate registers. When SCDAT is read, the read-only receive data register is accessed and when SCDAT is written, the write-only transmit data register is accessed.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 135
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI) REQUIRED
11.8.2 Serial Communications Control Register 1 (SCCR1)
$0048 Read: Write: Reset:
Bit 7 R8
6 T8
5 0
4 M
3 WAKE U
2 0
1 0
Bit 0 0
U
U
U
U
U
U
U
Figure 11-8. SCI Control Register 1 (SCCR1)
AGREEMENT
R8 -- Receive Data Bit 8 This bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0 - 7) are transferred from the serial receive shift register to the SCI receive data register. T8 -- Transmit Data Bit 8 This bit is the ninth data bit to be transmitted when the SCI system is configured for nine data bit operation (M = 1). When the eight low order bits (bits 0-7) of a transmit character are transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred to the ninth bit position of the shift register. M -- Mode (Select Character Format) The M bit controls the character length for both the transmitter and receiver at the same time. The 9th data bit is most commonly used as an extra stop bit or in conjunction with the "address mark" wake-up method. It can also be used as a parity bit. 1 = 1 start bit, 8 data bits + 9th data bit, 1 stop bit 0 = 1 start bit, 8 data bits, 1 stop bit WAKE -- Wake-up Mode Select 1 = Wake-up on address mark 0 = Wake-up on idle line
NON-DISCLOSURE
General Release Specification 136 Serial Communications Interface (SCI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Registers
11.8.3 Serial Communications Control Register 2 (SCCR2) The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI functions.
$0049 Read:
Bit 7 TIE
6 TCIE 0
5 RIE 0
4 ILIE 0
3 TE 0
2 RE 0
1 RWU 0
Bit 0 SBK 0
Write: Reset: 0
Figure 11-9. SCI Control Register 2 (SCCR2) TIE -- Transmit Interrupt Enable 1 = SCI interrupt if TDRE = 1 0 = TDRE interrupts disabled TCIE -- Transmit Complete Interrupt Enable 1 = SCI interrupt if TC = 1 0 = TC interrupts disabled RIE -- Receiver Interrupt Enable 1 = SCI interrupt if RDRF or OR = 1 0 = RDRF and OR interrupts disabled ILIE -- Idle Line Interrupt Enable 1 = Idle Line Interrupt Enable 0 = IDLE interrupts disabled TE -- Transmitter Enable When the transmit enable bit is set, the transmit shift register output is applied to the TDO line. Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software sets the TE bit from a cleared state. After loading the last byte in the serial communications data register and receiving the TDRE flag, the user can clear TE. Transmission of the last byte will then be completed before the transmitter gives up control of the TDO pin. While the transmitter is active, the Port C bit 7 line is forced to be an output.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI)
General Release Specification 137
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RE -- Receiver Enable When the receiver enable bit is set, the receiver is enabled. When RE is clear, the receiver is disabled and all of the status bits associated with the receiver (RDRF, IDLE, OR, NF and FE) are inhibited. While the receiver is enabled, the Port C bit 6 is forced to be an input. RWU -- Receiver Wake-up When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables the wake-up function. If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M = 1) consecutive ones. If the WAKE bit is set, RWU is cleared by the SCI logic after receiving a data word whose MSB is set. SBK -- Send Break If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. If the transmitter is currently empty and idle, setting and clearing SBK is likely to queue two character times of break because the first break transfers almost immediately to the shift register and the second is then queued into the parallel transmit buffer.
NON-DISCLOSURE
AGREEMENT
11.8.4 Serial Communications Status Register (SCSR) The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt.
$004A Read: Write: Reset:
Bit 7 TDRE
6 TC
5 RDRF
4 IDLE
3 OR
2 NF
1 FE
Bit 0 0
1
1
0
0
0
0
0
0
Figure 11-10. SCI Status Register (SCSR)
General Release Specification 138 Serial Communications Interface (SCI)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Registers
TDRE -- Transmit Data Register Empty Flag This bit is set when the byte in the transmit data register is transferred to the serial shift register. New data will not be transmitted unless the SCSR register is read before writing to the transmit data register. Reset sets this bit. TC -- Transmit Complete Flag This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous MARK). Reset sets this bit. RDRF --- Receive Data Register Full Flag This bit is set when the contents of the receiver serial shift register is transferred to the receiver data register. IDLE -- Idle Line Detected Flag This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven consecutive `1's). This bit will not be set by the idle line condition when the RWU bit is set. Once cleared, IDLE will not be set again until after RDRF has been set, (until after the line has been active and becomes idle again). OR -- Overrun Error Flag This bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared. NF -- Noise Error Flag This bit is set if there is noise on a "valid" start bit, any of the data bits, or on the stop bit. The NF bit is set during the same cycle as the RDRF bit but does not get set in the case of an overrun (OR). FE -- Framing Error Flag This bit is set when the word boundaries in the bit stream are not synchronized with the receiver bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE bit reflects the status of the byte in the receive data register and the transfer from
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI) General Release Specification 139
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REQUIRED
Serial Communications Interface (SCI) REQUIRED
the receive shift register to the receive data register is inhibited in the case of overrun. The FE bit is set during the same cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits further transfer of data into the receive data register until it is cleared.
11.8.5 Baud Rate Register (BAUD) The baud rate register (BAUD) is used to set the bit rate for the SCI system. Normally this register is written once, during initialization, to set the baud rate for SCI communications. Both the receiver and the transmitter use the same baud rate which is derived from the MCU bus rate clock. A two stage divider is used to develop custom baud rates from normal MCU crystal frequencies so it is not necessary to use special baud rate crystal frequencies.
AGREEMENT
$004B Read: Write:
Bit 7 0
6 SPP
5 SCP1 0
4 SCP0
3 0
2 SCR2
1 SCR1 U
Bit 0 SCR0 U
TCLR 1 1 0
RCKB 0 U
NON-DISCLOSURE
Reset:
Figure 11-11. SCI Baud Rate Register (BAUD) TCLR -- Clear Baud Rate Counters (for test purposes only) This bit is disabled and remains low in any mode other than test or bootstrap mode. Reset clears this bit. While in test or bootstrap mode, setting this bit causes the baud rate counter chains to be reset. The logic one state of this bit is transitory and reads always return a logic zero. This control bit is intended only for factory testing of the MCU. SPP -- SPI Prescaler bit 1 = SCI receiver clock connected to the SPI clock input. 0 = bus clock connected to the SPI clock input. The SCI baud rate can be calculated from the internal bus clock and the two prescaler factors PRS1 and PRS2. The first prescaler factor PRS1 is selected with SCP0 and SCP1, as shown in Table 11-1. The
General Release Specification 140 Serial Communications Interface (SCI) MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Serial Communications Interface (SCI) Registers
second prescaler factor PRS2 is selected with SCR0, SCR1 and SCR2, as shown in Table 11-2. The SCI baud rate B equals the internal bus clock divided by 16 divided by PRS1 divided by PRS2, [B = bus clock: 16: PRS1: PRS2]. SCP1, SCP0 -- First Serial Prescaler Select bits
Table 11-1. First Prescaler Stage
SCP1
0 0 1 1
SCP0
0 1 0 1
PRS1
1 3 4 13
SCR2, SCR1, SCR0 -- SCI Rate Select bits of the second prescaler stage These three bits select the baud rates for both the transmitter and the receiver.
Table 11-2. Second Prescaler Stage
SCR2
0 0 0 0 1 1 1 1
SCR1
0 0 1 1 0 0 1 1
SCR0
0 1 0 1 0 1 0 1
PRS2
1 2 4 8 16 32 64 128
RCKB -- SCI Receive Baud Rate Clock Test This bit is disabled and remains low in any mode other than test or bootstrap modes. Reset clears this bit. While in test or bootstrap mode, this bit may be written but not read (reads always return a logic zero). Setting this bit enables a baud rate counter test mode where
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Serial Communications Interface (SCI) General Release Specification 141
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the exclusive-or of the receiver clock (16 times the baud rate) and the transmit clock (1 times the baud rate) is driven out the PC3/TDO pin. This control bit is intended only for factory testing of the MCU.
11.9 SCI During WAIT Mode
The SCI system is not affected by the WAIT mode and continues regular operation. Any valid SCI interrupt will wake the system up.
NON-DISCLOSURE
General Release Specification 142 Serial Communications Interface (SCI)
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 12. Analog to Digital Converter
12.1 Contents
12.2 12.3 12.4 12.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Internal and Master Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 145
12.6 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6.1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 146 12.6.2 A/D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7 12.8 A/D During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Analog to Digital Converter
General Release Specification 143
NON-DISCLOSURE
12.9 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 150 12.9.1 Transfer Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.2 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.3 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.4 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.5 Gain Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.6 Differential Linearity Error . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.7 Integral Linearity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.8 Total Unadjusted Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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REQUIRED
Analog to Digital Converter REQUIRED 12.2 Introduction
The Analog to Digital converter system consists of a single 8-bit successive approximation converter and a channel multiplexer. There is one 8-bit result data register and one 8-bit status/control register. The reference supply for the converter uses two dedicated pins rather than being driven by the system power supply lines, because the voltage drops in the bonding wires of such heavily loaded pins would decrease the accuracy of the A/D conversion. An internal RC type oscillator is activated by the ADRC bit in the A/D status/control register. This RC oscillator is used to give sufficiently high clock rate to the A/D when the bus speed is too low for the A/D to be accurate. Additionally, the ADON bit allows the user to disconnect the A/D when not used, in order to save power. This is particularly useful to reduce current consumption (by typically 100A) when going into the WAIT mode. The A/D is ratiometric and two dedicated pins supply the reference voltage (VREFH and VREFL). An input voltage equal to or greater than VREFH converts to $FF (full scale) with no overflow indication (if greater). An input voltage equal to VREFL converts to $00. For ratiometric conversions, the source of each analog input should use VREFH as the supply voltage and be referenced to VREFL.
NON-DISCLOSURE
AGREEMENT 12.3 A/D Principle
The A/D reference inputs are applied to a precision internal digital to analog converter. Control logic drives this D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. The conversion is monotonic with no missing codes. The 8-bit conversions are accurate to within 1.5 LSB including quantization.
General Release Specification 144 Analog to Digital Converter
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Analog to Digital Converter A/D Operation
12.4 A/D Operation
The A/D is an 8-bit S.A.R. type A/D converter, with continuous conversion per given channel. The result of a conversion is loaded into the read-only result data register, and a conversion complete flag COCO is set in the A/D status/control register. Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared. Thus the A/D is disabled. Each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 MHz. A multiplexer allows the single A/D converter to select one of four external analog signals and three internal reference sources.
12.5 Internal and Master Oscillator
If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by setting the ADRC bit in the A/D status/control register to 1. When the internal RC oscillator is being used as the conversion clock three limitations apply: 1. The conversion complete flag (COCO) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the RC oscillator and its asynchronism with regard to the MCU bus clock. 2. The conversion process runs at the nominal 1.5 MHz rate, but the conversion results must be transferred to the MCU result registers synchronously with the MCU bus clock, so the conversion time is limited to a maximum of one channel per bus cycle. 3. If the system clock is running faster than the RC oscillator, the RC oscillator should be turned off, and the system clock used as the conversion clock.
General Release Specification Analog to Digital Converter 145
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
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AGREEMENT
REQUIRED
Analog to Digital Converter REQUIRED 12.6 A/D Registers
12.6.1 A/D Status and Control Register (ADSCR)
$004F Read: Write:
Bit 7 COCO
6 ADRC
5 ADON 0
4 0
3 CH3
2 CH2 0
1 CH1 0
Bit 0 CH0 0
AGREEMENT
Reset:
0
0
0
0
Figure 12-1. A/D Status and Control Register (ADSCR) COCO -- Conversions Complete This read-only status bit is set when a conversion is completed, indicating that the A/D data register contains valid results. This bit is cleared whenever the A/D status/control register is written and a new conversion automatically started, or whenever the A/D register is read. Once a conversion has been started by writing to the A/D status/control register, conversions of the selected channel will continue every 32 cycles until the A/D status/control register is written to again. In this continuous conversion mode the A/D data register will be filled with new data, and the COCO bit set, every 32 cycles. Data from the previous conversion will be overwritten regardless of the state of the COCO bit prior to writing. ADRC -- RC Oscillator On When ADRC is set, the A/D section runs on the internal RC oscillator instead of the CPU clock. The RC oscillator requires a time tRCON to stabilize, and results can be inaccurate during this time. See Section 12.5 Internal and Master Oscillator. ADON -- A/D On When the A/D is turned on (ADON = 1), it requires a time tADON for the current sources to stabilize, and results can be inaccurate during this time. This bit turns on the charge pump.
NON-DISCLOSURE
General Release Specification 146 Analog to Digital Converter
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Analog to Digital Converter A/D Registers
Table 12-1. A/D Clock Selection
ADRC
0 0 1 1
ADON
0 1 0 1
Comments
RC oscillator off, A/D converter off. RC oscillator off, A/D converter on. RC oscillator on, A/D converter off. Gives time for the RC osc to stabilize. RC oscillator on, A/D converter on.A/D using RC osc clocks
CH3, CH2, CH1 and CH0 form a four bit field which is used to select one of sixteen A/D channels. Channels 4-15 are used for internal reference points. The following table shows the signals selected by the channel select field.
Table 12-2. A/D Channel Assignments
CH3
0 0 0 0 0 0 0 0 1 1 1 1 1
CH2
0 0 0 0 1 1 1 1 0 0 0 0 1
CH1
0 0 1 1 0 0 0 1 0 0 1 1 X
CH0
0 1 0 1 0 1 0 1 0 1 0 1 X
Channel
0 1 2 3 4 5 6 7 8 9 10 11 12-15
Signal
AN0 AN1 AN2 AN3 VREFL VREFL VREFL VREFL VREFH (VREFH+VREFL)/2 VREFL VREFL VREFL
NOTE:
Performing a digital read of the A/D input with levels other than VDD or VSS on the ADIN pins will result in greater power dissipation during the read cycle, and may give hazardous results on the ADIN input
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Analog to Digital Converter
General Release Specification 147
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CH3-0 -- Channel Select Bit
REQUIRED
Analog to Digital Converter REQUIRED
12.6.2 A/D Data Register One 8-bit result register is provided. This register is updated each time COCO is set.
$004E Read: Write: Reset: U U U U U U U U Bit 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 Bit 0 bit 0
AGREEMENT
Figure 12-2. A/D Data Register (ADDR)
12.7 A/D During WAIT Mode
The A/D converter continues normal operation during WAIT mode. To decrease power consumption during WAIT, it is recommended that both the ADON and ADRC bits in the A/D status/control register be cleared if the A/D converter is not being used. If the A/D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit be cleared.
NOTE:
NON-DISCLOSURE
As the A/D converter continues to function normally in WAIT mode, the COCO bit is not cleared.
12.8 Analog Input
The external analog voltage value to be converted by the A/D converter is sampled on an internal capacitor through a resistive path provided by input-selection switches and a sampling aperture time switch. Sampling time is limited to 12 bus clock cycles. After sampling, the analog value is stored on a capacitor and held until the end of conversion. During this hold time, the analog input is disconnected from the internal A/D system and the external voltage source sees a high impedance input. The equivalent analog input during sampling is a RC low-pass filter with resistance around 50 K and a capacitance of around 10pF. (It should be noted that these are typical values measured at room temperature).
General Release Specification 148 Analog to Digital Converter
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Analog to Digital Converter Analog Input
ANALOG INPUT
INPUT PROTECTION
DIFFUSION
*
< 2pF
+~ 20 V
> 50 K DAC CAPACITANCE
10 pF
VREFL / VSS
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME
Figure 12-3. Electrical Model of an A/D Input Pin
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Analog to Digital Converter
General Release Specification 149
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REQUIRED
Analog to Digital Converter REQUIRED 12.9 Conversion Accuracy Definitions
This section explains the terminology used to specify the analog characteristics of the A/D converter. 12.9.1 Transfer Curve The ideal transfer curve can be thought of as a staircase of uniform step size with perfect positioning of the endpoints. Figure 12-4 shows the ideal transfer curve of an 8-bit A/D converter.
$FF
AGREEMENT
$FE
CONVERSION RESULT
$FD
1-BIT ACCURACY
$03
NON-DISCLOSURE
$02
$01
$00 1 2 3 253 254 255
INPUT VOLTAGE (LSB) 1LSB = VREFH / 256
Figure 12-4. Transfer Curve of an Ideal 8-Bit A/D Converter 12.9.2 Monotonicity The characteristic of the transfer function whereby increasing the input signal results in the output never decreasing.
General Release Specification 150 Analog to Digital Converter MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Analog to Digital Converter Conversion Accuracy Definitions
12.9.3 Quantization Error Also known as digitization error or uncertainty. It is the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input.
12.9.4 Offset Error The offset error is the DC shift of the entire transfer curve of an ideal converter.
12.9.5 Gain Scale Error The gain error is an error in the input to output transfer ratio. Gain error causes an error in the slope of the transfer curve.
12.9.6 Differential Linearity Error The differential linearity error is the difference between actual analog voltage change and the ideal (1LSB) voltage change at any code change.
12.9.7 Integral Linearity Error The integral linearity error is the departure from the best fitting line through all A/D code changes. This error is not specified from the ideal line to make this error independent from offset and gain errors causes an error in the slope of the transfer curve.
12.9.8 Total Unadjusted Error The total unadjusted error is the maximum error that occurs without adjusting offset and gain errors. This error is a combination of offset, scale and integral linearity errors.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Analog to Digital Converter
General Release Specification 151
NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog to Digital Converter REQUIRED NON-DISCLOSURE
General Release Specification 152 Analog to Digital Converter
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 13. EEPROM
13.1 Contents
13.2 13.3 13.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . . . 154 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . . . 155
13.5 EEPROM Read, Erase and Programming Procedures . . . . . 156 13.5.1 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.2 Erase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.3 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.6 Operation in WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.2 Introduction
The EEPROM on this device is 256 bytes and is located from address $0400 to $04FF. Programming the EEPROM can be done by the user on a single-byte basis by manipulating the EEPROM control register (EEPCR). An erased byte reads as `FF' and any programmed bit reads as `0'.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EEPROM
General Release Specification 153
NON-DISCLOSURE
AGREEMENT
REQUIRED
EEPROM REQUIRED 13.3 EEPROM Control Register (EEPCR)
$001C Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 EEOSC EER1 EER0 EELAT EEPGM 4 3 2 1 Bit 0
Figure 13-1. EEPROM Control Register (EEPCR) EEOSC -- EEPROM RC Oscillator Control
AGREEMENT
When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. After setting the EEOSC bit, delay a time tRCON to allow the RC oscillator to stabilize. This bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5 MHz. Reset clears this bit. EER1, EER0 -- Erase Select Bits EER1 and EER0 form a 2-bit field which is used to select one of three erase modes: byte, block, or bulk erase. Table 13-1 shows the modes selected for each bit configuration. These bits are readable and writable and are cleared by reset. In byte erase mode, only the selected byte is erased. In block mode, a 128-byte block of EEPROM is erased. The EEPROM memory space is divided into two 128-byte blocks ($0400-$047F, $0480-$04FF), and doing a block erase to any address within a block will erase the entire block. In bulk erase mode, the entire 256 byte EEPROM section is erased. A block protect function is available on block 2 of the EEPROM memory space. See Section 13.4 EEPROM Options Register (EEOPR) for more details. Table 13-1. Erase Mode Select
EER1
0 0 1 1
NON-DISCLOSURE
EER0
0 1 0 1
MODE No Erase Byte Erase Block Erase (block1 or block2) Bulk Erase (block1 & block2)
General Release Specification 154 EEPROM
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
EEPROM EEPROM Options Register (EEOPR)
EELAT -- EEPROM Programming Latch The EELAT bit is the EEPROM programming latch enable. When EELAT is at `zero', the EER1, EER0 and EEPGM bits are reset to zero. When the EELAT bit is clear, data can be read from the EEPROM, and when set, this bit allows the address and data to be latched into the EEPROM for further programming or erase operation. Address and data can only be latched when the EEPGM bit is at `zero'. Reset and power-on reset, reset the EELAT bit. EEPGM -- EEPROM Programming Power Enable EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, power is switched off. This enables pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be set if EELAT=1. If EELAT is not set, then EEPGM cannot be set. EELAT=0 or reset clears the EEPGM bit.
13.4 EEPROM Options Register (EEOPR)
This register contains the secure and protect functions for the EEPROM and allows the user to select options in a non-volatile manner. The contents of the EEOPR register are loaded into data latches with each power-on or external reset. The register is implemented in EEPROM, therefore reset has no effect on the individual bits.
$0400 Read:
Bit 7
6
5
4
3
2
1 EEPRT
Bit 0
Write: Reset: 0 0 0 0 0 0 0 0
Figure 13-2. EEPROM Options Register (EEOPR)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EEPROM
General Release Specification 155
NON-DISCLOSURE
AGREEMENT
REQUIRED
EEPROM REQUIRED
EEPRT -- EEPROM Protect Bit In order to achieve a higher degree of protection, the EEPROM is split into two 128-byte blocks. Block 1 cannot be protected. Block 2 is protected by the EEPRT bit of the options register. When this bit is set from 0 to 1 (erased), the protection remains until the next power-on or external reset. EEPRT can only be written to `0' when the ELAT bit in the EEPROM control register is set. 1 = Block 2 of the EEPROM array is not protected; all 256 bytes of EEPROM can be accessed for any read, erase or programming operations 0 = Block 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful
AGREEMENT
13.5 EEPROM Read, Erase and Programming Procedures
13.5.1 Read Procedure To read data form EEPROM, the EELAT bit must be clear. EEPGM, EER1 and EER0 are all forced to zero. EEPROM is read as if it were a normal ROM. The charge pump generator is off since EEPGM is zero. If a read is performed while ELAT is set, data will be read as $FF.
NON-DISCLOSURE
13.5.2 Erase Procedure There are three types of ERASE operation mode see Table 13-1, byte erase, block erase or bulk erase. To erase a byte of EEPROM: set EELAT = 1, ER1 = 0 and ER0 = 1, write to the address to be erased, and set EEPGM for a time tEBYTE. To erase a block of EEPROM: set EELAT = 1, ER1 = 1 and ER0 = 0, write to any address in the block, and set EEPGM for a time tEBLOC. For a bulk erase: set EELAT = 1, ER1 = 1, and ER0 = 1, write to an address in the array with A0 or A1 = `1', and set EEPGM for a time tEBULK.
General Release Specification 156 EEPROM
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
EEPROM Operation in WAIT
13.5.3 Programming Procedure To program the content of EEPROM, set EELAT bits, write data to the desired address, and set the EEPGM bit. After the required programming delay tEEPGM, EELAT must be clear, which also resets EEPGM. During a programming operation, any access to EEPROM will return $FF. To program a second byte, EELAT must be cleared before it is set, or the programming will have no effect.
NOTE:
13.6 Operation in WAIT
The user may want to ensure that the RC oscillator is disabled before entering WAIT mode to help conserve power.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EEPROM
General Release Specification 157
NON-DISCLOSURE
AGREEMENT
Each byte must be erased before reprogramming. Do not use overprogramming (write more `zeros').
REQUIRED
EEPROM REQUIRED NON-DISCLOSURE
General Release Specification 158 EEPROM
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 14. Pulse Width Modulator (PWM)
14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3.1 PWM Channel Microshifting . . . . . . . . . . . . . . . . . . . . . . . 161 14.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.4.1 PWM Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.4.2 PWM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4.3 PWM Channel Enable Register. . . . . . . . . . . . . . . . . . . . . 165 14.4.4 PWM Channel Polarity Register . . . . . . . . . . . . . . . . . . . . 165 14.5 PWM During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
14.2 Introduction
The pulse width modulator (PWM) system has eight 8-bit channels. Preceding the 8-bit (/256) PWM counter is a programmable prescaler.The PWM frequency is selected by choosing the desired divide option from the programmable prescaler. The four PWM channels 0 to 3 provide four full H-bridge drivers capable of driving air core instruments or stepper motor instruments. Each of the H-bridges will be implemented as a combination of one PWM power driver and another general purpose output (GPO) port power driver. A single PWM channel provides a pulse width ratio for the corresponding PWM driver part of a single H-bridge. Thus the current through the bridge can be controlled by the pulse width ratio. The four PWM channels 4 to 7 with their power drivers can support four 90 (small angle) aircore instruments.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Pulse Width Modulator (PWM)
General Release Specification 159
NON-DISCLOSURE
AGREEMENT
REQUIRED
Pulse Width Modulator (PWM) REQUIRED
fOP PRESCALER / 0.5,1,2,4,64 HC05 DATA BUS 8-BIT COUNTER (/256)
8-BIT COMPARATOR
RQ M S U QX
QM U QX GPO
AGREEMENT
PWM DATA REGISTER PWM DATA BUFFER PPOL SIGN PWME
PWMC0
PWMC1
PWM CONTROL, CHANNEL ENABLE AND CHANNEL POLARITY REGISTERS
Figure 14-1. PWM Block Diagram (one channel)
NON-DISCLOSURE
14.3 Functional Description
The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data register yields an `low' output (0%), but a $FF yields a duty of 255/256. To achieve the 100% duty (`high' output), the polarity control bit is set to zero while the data register has $00 in it. Figure 14-1 shows the block diagram of a PWM timer channel 0 to 3. The 8-bit counter runs at the rate of the selected clock source provided by the programmable prescaler. The counter is compared to the data register. When the counter matches the data register a flip-flop changes state causing the PWM output to also change state. When the PWM counter rolls over it resets the flip-flop and the output changes back. Notice that there is a select bit called PPOL which allows each channel to independently create a signal which is a low-to-high or high-to-low transition.
General Release Specification 160 Pulse Width Modulator (PWM)
PWMC2
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
RIGHT LEFT
GPO
Pulse Width Modulator (PWM) Functional Description
The SIGN bit in the PWM control register selects whether the left or the right port line (left or right path of an H-bridge) is enabled for the PWM signal. The opposite port line drives the general purpose output value. The SIGN bit performs also the inversion of the PWM signal. This is done because the duty values are assumed to be 2's complement values in the range from -256 to +255. A change from duty value $01FF to value $0000 (-1 to 0) causes a change of the current direction within the corresponding H-bridge. This is done by changing the polarity of the PWM signal and exchanging PWM and output port signals within the Hbridge.
14.3.1 PWM Channel Microshifting Switching more than one PWM channel simultaneously would cause large currents in the corresponding power drivers of the H-bridges. Clocking of different channels must be delayed such that only one channel switches at a time. Therefore microshifts are introduced to achieve a switching delay between different channels.
BUS CLOCK
CHANNEL 0 1/4TBUS CHANNEL 1 2/4TBUS CHANNEL 2
7/4TBUS CHANNEL 7
Figure 14-2. PWM Microshifts
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Pulse Width Modulator (PWM)
General Release Specification 161
NON-DISCLOSURE
AGREEMENT
REQUIRED
Pulse Width Modulator (PWM) REQUIRED
The start of the PWM period is shifted by a quarter of the period time of the bus clock tBUS for the channels 0 to 7. See Figure 14-2. Inevitable large currents due to switching of the power drivers are distributed over a number of time slots. They do not load power supply at the same time.
14.4 Registers
Associated with the PWM system, there are eight PWM data registers, a control/sign register, a channel enable register and a channel polarity register. The registers can be written to and read at any time. For updating the PWM values, the following sequence must be followed: 1. Write the corresponding SIGN bit in the PWM control register 2. Write data to the corresponding data register Not until after the data register is written are the SIGN bits transferred from a buffer to the SIGN register. Data written to a data register is held in a buffer and transferred to the PWM data register at the end of a PWM cycle. Reads of a data register will always result in the read of the PWM data buffer and not the PWM data register.
NON-DISCLOSURE
General Release Specification 162 Pulse Width Modulator (PWM)
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Pulse Width Modulator (PWM) Registers
14.4.1 PWM Data Registers The PWM system has eight 8-bit data registers which hold the duty cycle for each PWM output. The data bits in these registers are set by reset.
Bit 7 PWM0 $0010 PWM1 $0011 PWM2 $0012 PWM3 $0013 PWM4 $0014 PWM5 $0015 PWM6 $0016 PWM7 $0017 Read: bit 7 Write: Read: Write: Read: bit 7 Write: Read: bit 7 Write: Read: bit 7 Write: Read: bit 7 Write: Read: Write: Read: bit 7 Write: Reset: 1 1 1 1 1 1 1 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6 5 4 3 2 1 Bit 0
Figure 14-3. PWM Data Registers (PWM0-7)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Pulse Width Modulator (PWM)
General Release Specification 163
NON-DISCLOSURE
AGREEMENT
REQUIRED
Pulse Width Modulator (PWM) REQUIRED
14.4.2 PWM Control Register
$0018 Read: Write: Reset:
Bit 7 0
6 PWMC3
5 PWMC2 1
4 PWMC1 1
3 SIGN3 0
2 SIGN2 0
1 SIGN1 0
Bit 0 SIGN0 0
PWMRST 0 1
Figure 14-4. PWM Control Register (PWMCTL) PWMRST -- PWM Reset Writing `1' to the PWMRST bit resets the PWM counter. The PWMRST bit reads always as `0'. PWMC3-1 -- PWM Clock Rate These bits select the input clock rate and determines the period as shown in Figure 14-1. The PWM prescaler clock input is fOP, which is the bus frequency. Table 14-1. PWM Clock Rate
PWMC3
0
AGREEMENT
PWMC2
0 0 1 1 0 0 1 1
PWMC1
0 1 0 1 0 1 0 1
PWM Clock
2 x fOP fOP fOP / 2 fOP / 4 fOP / 64
PWM OUT
fOP / 128 fOP / 256 fOP / 512 fOP / 1024 fOP / 16384
NON-DISCLOSURE
0 0 0 1 1 1 1
PWM Shut off - to save power if the PWM is not used
SIGN3-0 -- Sign of the PWM Channel 0-3 The SIGN bit selects whether the left or the right output is the PWM signal. The opposite output is the general purpose port. The SIGN bit performs also the inversion of the PWM signal. See Figure 7-4 for the assignment of the PWM channels to the power driver lines. 1 = Right PWM output 0 = Left PWM output
General Release Specification 164 Pulse Width Modulator (PWM)
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Pulse Width Modulator (PWM) Registers
14.4.3 PWM Channel Enable Register
$0019 Read:
Bit 7 PWME7
6 PWME6 0
5 PWME5 0
4 PWME4 0
3 PWME3 0
2 PWME2 0
1 PWME1 0
Bit 0 PWME0 0
Write: Reset: 0
Figure 14-5. PWM Channel Enable Register (PWMEN) PWME7-0 -- PWM Channel Enable These bits enable/disable the corresponding PWM channels. If a bit is disabled, the corresponding pin functions as a general purpose output (GPO). Refer to Section 7.7 Port E and Port F (Power Drivers). 1 = The PWM channel is enabled. 0 = The PWM channel is disabled and the corresponding lines are general purpose outputs (GPO)
14.4.4 PWM Channel Polarity Register
Read: PPOL7 Write: Reset: 0 0 0 0 0 0 0 0 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Figure 14-6. PWM Channel Polarity Register (PWMPOL) PPOL7-0 -- PWM Polarity These bits initialize the corresponding PWM outputs. 1 = PWM channel is high at the beginning of the period, then toggles to low when the data count is reached. 0 = PWM channel is low at the beginning of the period, then toggles to high when the data count is reached.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Pulse Width Modulator (PWM)
General Release Specification 165
NON-DISCLOSURE
$001A
Bit 7
6
5
4
3
2
1
Bit 0
AGREEMENT
REQUIRED
Pulse Width Modulator (PWM) REQUIRED 14.5 PWM During WAIT Mode
The PWM continues normal operation during WAIT mode. To decrease power consumption during WAIT, the PWM should be shut off prior to entering WAIT mode by setting the corresponding bits in the PWM control register. Refer to Section 7.8 Port E and Port F During WAIT Mode for information about the corresponding ports.
NON-DISCLOSURE
General Release Specification 166 Pulse Width Modulator (PWM)
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 15. EPROM
15.1 Contents
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.3 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.4.1 EPROM Programming Register (EPROG) . . . . . . . . . . . . 170 15.5 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . 171
15.2 Introduction
The HC705H12 contains 12K EPROM instead of ROM and the mask options are controlled by a programmable nonvolatile mask option register (MOR). The MOR is an EPROM register which must be programmed appropriately prior to operation of the micro-controller.
15.3 EPROM Bootloader
Bootloader programming mode is entered upon the rising edge of RESET if the IRQ/VPP pin is at VTST and the PB0 pin is at logic one (refer to Table 6-1). The bootloader code resides in the ROM from $3F00 to $3FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The user code must be a one-to-one correspondence with the internal EPROM addresses (including the MOR).
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EPROM
General Release Specification 167
NON-DISCLOSURE
AGREEMENT
REQUIRED
EPROM REQUIRED
15.3.1 Bootloader Functions Two pins are used to select various bootloader functions. These pins are PB2 and PB3. Two other pins, PB7 and PB6 are used to drive the PROG LED and the VERF LED respectively. The programming modes are shown in Table 15-1.
Table 15-1. Bootloader Functions
PB2
0 0 1 1
AGREEMENT
PB3
0 1 0 1
MODE
Program/Verify EPROM Verify only Jump to RAM Load RAM and Execute
The bootloader uses an external 14 bit counter to address the memory device containing the code to be copied. This counter requires a clock (provided at PB5) and a reset signal (provided at PB4).
NOTE:
The EPROM must be erased before performing a program cycle.
For the communication with a host computer via a standard RS-232 interface PB1 is used as transmitter (TX) and PB0 is used as receiver (RX).
NON-DISCLOSURE
General Release Specification 168 EPROM
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
EPROM EPROM Bootloader
L1 - VERIFY L2 - PROGRAM
+5V L1 470
+5V L2 +5V 470 10K 10K +5V
PB6
PB7
PB5 PB4
CLOCK
+5V
RESET VDD VREFH
+5V
S3 +5V +5V
VCC
RST
CLK
AVDD TCAP0 TCAP1 TCAP2 TCAP2
S2
VPP PGM
MC68HC705H12
PB2
S1
PB3
A0 A1
Q0 Q1 Q2 Q3 VDD
27128 (16K EPROM)
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
D0 D1 D2 D3 D4 D5 D6 D7
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 VSS
MC74HC393
Q4
VPP
IRQ/VPP CE VSS OE VSS OSC1 1MHz OSC2
A12 A13
20 pF
20 pF
Figure 15-1. MC68HC705H12 Programming Circuit
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EPROM General Release Specification 169
NON-DISCLOSURE
AGREEMENT
RESET
10K
10K
REQUIRED
EPROM REQUIRED 15.4 EPROM Programming
The EPROM array is programmed through manipulation of the programming register located at $001D. It may be programmed in user, bootstrap or test mode. In addition to the main EPROM array, the mask option register must also be programmed appropriately by the programming software.
15.4.1 EPROM Programming Register (EPROG)
AGREEMENT
$001D Read:
Bit 7
6
5
4
3
2 ELAT
1
Bit 0 EPGM
Write: Reset: 0 0 0 0 0 0 0 0
Figure 15-2. EPROM Programming Register (EPROG) ELAT -- EPROM Latch Control This read/write bit controls the latching of the address and data buses when programming the EPROM. 1 = Address and data buses are latched when the following instruction is a write to one of the EPROM locations. Normal reading is disabled if ELAT =1 0 = EPROM address and data buses are configured for normal reading EPGM -- EPROM Program Control This read/write bit controls whether the programming voltage is applied to the EPROM array. For programming, this bit can only be set if the LATCH bit has been previously set. Both EPGM and ELAT cannot be set in the single write. 1 = Programming voltage applied to EPROM array 0 = Programming voltage not applied to EPROM array
NON-DISCLOSURE
General Release Specification 170 EPROM
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
EPROM Mask Option Register (MOR)
The sequence for programming the EPROM is as follows: 1. Set the ELAT bit. 2. Write the data to be programmed to the EPROM (or MOR byte) location to be programmed. 3. Set the EPGM bit. 4. Wait a time tEPGM 5. Clear the ELAT and EPGM bits. 6. Repeat for each byte.
15.5 Mask Option Register (MOR)
The mask option register (MOR) is used to select all mask options available on the MC68HC705H12. When in the erased state, the EPROM cells read as a logic zero which therefore represents the value transferred from the MOR at reset if it is left unprogrammed. The unimplemented bits of this register are read as `0'. There are two mask option registers (MOR1, MOR2) implemented. MOR2 is used only.
Bit 7 MOR1 $3EFE MOR2 $3EFF Read: Write: Read: PWDRW Write: Reset: 0 0 0 0 0 0 0 0 COPE 6 5 4 3 2 1 Bit 0
Figure 15-3. Mask Options Registers (MOR1 and MOR2) PWDRW -- Ports E/F in WAIT mode 1 = Ports E/F continue in WAIT (enabled) 0 = Ports E/F are forced `low' in WAIT (disabled) COPE -- COP Timer Enable 1 = COP timer enabled. 0 = COP timer disabled.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA EPROM
General Release Specification 171
NON-DISCLOSURE
AGREEMENT
REQUIRED
EPROM REQUIRED NON-DISCLOSURE
General Release Specification 172 EPROM
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 16. Electrical Characteristics
16.1 Contents
16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 176 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 178 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.10 Power Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.11 Power-on Reset/Low Voltage Reset Characteristics . . . . . . . 181
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Electrical Characteristics
General Release Specification 173
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Characteristics REQUIRED 16.2 Maximum Ratings
(Voltage referenced to VSS)
Rating Supply Voltage Supply Voltage for Power Drivers Input Voltage Normal Operation Monitor Mode (IRQ Pin Only) Current Drain Per Pin Short Circuit Time for Power Drivers (PE7-0, PF3-0) (note 1) Operating Temperature Range Storage Temperature Range Write/Erase Cycles EEPROM Data Retention EEPROM
1.
Symbol VDD PVDD1,2 VIN VIN IOmax
Value -0.3 to +7.0 -0.3 to +10.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to 2 x VDD + 0.3 300
Unit V V V V mA
AGREEMENT
tSC TA TSTG
20 -40 to +85 -65 to +150 10,000 10
ms C C cycles years
Only one output shorted for a time.
NON-DISCLOSURE
Stresses above those listed as `maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Unused inputs are connected to the appropriate voltage level, either VSS or VDD. Positive current flow is defined as conventional current flow into the device. Negative current flow is defined as current flow out of the device.
General Release Specification 174 Electrical Characteristics
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Electrical Characteristics Thermal Characteristics
16.3 Thermal Characteristics
Characteristic Thermal Resistance PLCC(52 pin) Symbol JA Value 50 Unit C/W
16.4 Power Considerations
The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following equation:
T J = T A + ( P D * JA )
[1]
where: TA = Ambient temperature (C) JA = Package thermal resistance, junction-to-ambient (C/W) PD = PINT + PI/O (W) PINT = Internal chip power = IDD * VDD (W) PI/O = Power dissipation on input and output pins (user determined) An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = ---------------------T J + 273
[2]
Solving equations [1] and [2] for K gives:
2 K = P D * ( T A + 273 ) + JA * P D
[3]
where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA by solving the above equations. The package thermal characteristics are shown in Section 16.3 Thermal Characteristics.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Electrical Characteristics
General Release Specification 175
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Characteristics REQUIRED 16.5 DC Electrical Characteristics
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
Characteristic Output Voltage ILOAD = -10 A ILOAD = +10 A Output High Voltage ILOAD = -0.8 mA PA7-0, PB7-0, PC7-0 ILOAD = -80 A OSC2 Output Low Voltage ILOAD = 1.6 mA PA7-0, PB7-0, PC7-0, RESET ILOAD = 80 A OSC2 Output Source Current (see maximum ratings) VO = 4.5 V (VDD = 5V) VO = 4.0 V (VDD = 5V) PA7-0, PB7-0, PC7-0 Output Sink Current (see maximum ratings) VO = 0.5 V (VDD = 5V) VO = 1.0 V (VDD = 5V) PA7-0, PB7-0, PC7-0 Input High Voltage PA7-0, PB7-0, PC7-0, PD3-0, IRQ, RESET, OSC1 Input Low Voltage PA7-0, PB7-0, PC7-0, PD3-0, IRQ, RESET, OSC1 Supply current (note 2) Run (fOP = 2.1 MHz) Run (fOP = 525 kHz, Slow Mode) Wait (fOP = 2.1 MHz) Wait (fOP = 525 kHz, Slow Mode) IO Ports Hi-Z Leakage Current PA7-0, PB7-0, PC7-0 Input Current PD3-0, IRQ, OSC1, VREFH
Symbol VOH VOL
Min VDD - 0.1 --
Typ 1 -- --
Max -- 0.1
Unit V
VOH
VDD - 0.8 VDD - 0.8
-- --
-- --
V V
AGREEMENT
VOL
-- -- -1.0 -3.0
-- -- -- --
0.4 0.4 -14.5 -26.0
V V mA mA
IOH
IOL
5.0 10.0
-- --
15.0 27.0
mA mA
NON-DISCLOSURE
VIH
0.7 x VDD
--
VDD
V
VIL VSS IDD IDD IDD IDD IIL IIN -- -- -- -- -- -- -- 7 -- 3 1 -- --
0.2 x VDD 10 7 6 4 1 1
V mA mA mA mA A A
General Release Specification 176 Electrical Characteristics
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Electrical Characteristics DC Electrical Characteristics
Characteristic Schmitt Trigger Inputs - Hysteresis PA7-0, PB7-5, PC6, PC3-0, IRQ, RESET Internal Pullup Resistor RESET Injection Current (note 3) PA7-0 PB7-2 PC7-0 PD3-0 PE7-0 PF3-0 Data Retention Supply Voltage (note 5) Oscillator transconductance (IOSC2/VOSC1)
1. 2. 3.
Symbol VHYRS RRSTPU
Min 0.3 8
Typ 1 -- 11
Max 1.5 14
Unit V K
IINJ
--
--
VDR gm
2 1.1 -- --
V mA/V
4. 5.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Electrical Characteristics
General Release Specification 177
NON-DISCLOSURE
Typical values reflect average measurements at midpoint of voltage range at 25 C. Test Conditions: All I/O Ports are configured as output with no DC load. External Clock Input OSC1 is driven by square wave external clock. A simple protection can be built with a series resistor: R > VMAX /IINJ The sum of currents during multiple injection should be limited below the maximum values for a single pin: R > (VMAX /IINJ)*(number of pins). The A/D conversion accuracy can degrade to 7LSB on a channel adjacent to the one subjected to current injection. Not production tested. The Enabling of the LVR by mask option will cause a permanent current trough the LVR circuitry. The MCU retains RAM contents and CPU register contents.
AGREEMENT
10 10 10 1 10 10
mA
REQUIRED
Electrical Characteristics REQUIRED 16.6 Control Timing
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
Characteristic Oscillator Frequency Crystal / Ceramic Resonator External Clock Source Internal Operating Frequency (fOSC / 2) Crystal / Ceramic Resonator External Clock Cycle Time (1 / fOP) RESET Pulse Width IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period OSC1 Pulse Width
Symbol fOSC
Min -- dc -- dc 476 1.5 120 --(1) 100
Max 4.2 4.2 2.1 2.1 -- -- -- -- --
Unit MHz MHz MHz MHz ns tCYC ns tCYC ns
fOP tCYC tRL tILIH tILIL tOH,tOL
AGREEMENT
1. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC.
16.7 A/D Converter Characteristics
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
NON-DISCLOSURE
Characteristic Resolution Monotonicity Quantization Error Offset Error Gain Error Differential Linearity Error Integral Linearity Error
Parameter Number of bits resolved by the A/D Conversion result never decreases with an increase in input voltage and has no missing codes Uncertainly due to converter resolution DC shift of the entire transfer curve of an ideal converter (1) Difference between the actual and expected gain (end point to end point) (1) Difference between the actual analog voltage change and the ideal voltage change (1) Max deviation from the best straight line through the A/D transfer characteristics (1)
Min 8
Max -- GUARANTEED
Unit Bit
-- -- -- -- --
1/2 1/2 1/2 1/2 1/2
LSB LSB LSB LSB LSB
General Release Specification 178 Electrical Characteristics
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Electrical Characteristics EEPROM Characteristics
Characteristic Absolute Accuracy / Total Unadjusted Error Conversion Range VREFH Conversion Time Zero Input Reading Full Scale Reading (3) RC oscillator stabilization time tRCON ADC stabilization time tADON
1. AVDD = VREFH = VDD and VREFL = 0 V 2. For 8-bit resolution Vref 3.5V is necessary
Parameter Difference between the actual input voltage and the full-scale equivalent of the binary code output for all errors (1) Analog input voltage range Analog reference voltage (2) Total time to perform a single analog to digital conversion Conversion result when VIN = VSS Conversion result when VIN = VREFH
Min -- VSS VSS -- 00 --
Max 1.5 VREFH VDD + 0.1 32 -- FF 5 100
Unit LSB V V cycles Hex Hex s s
3. When VIN > VREFH Conversion result will be `FF' (for the max input voltage VIN see maximum ratings)
16.8 EEPROM Characteristics
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
Characteristic EEPROM Byte Programming Time EEPROM Byte Erase Time EEPROM Block Erase Time EEPROM Bulk Erase Time RC oscillator stabilization time
Symbol tEEPGM tEBYTE tEBLOC tEBULK tRCON
Min 10 10 10 20 --
Max 10 10 50 50 5
Unit ms ms ms ms s
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Electrical Characteristics
General Release Specification 179
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Characteristics REQUIRED 16.9 EPROM Characteristics
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
Characteristic EPROM Programming Voltage Rate1 EPROM Programming Time EPROM Data Retention
1. Typical value = 12 - 15 V.
Symbol
VPP tEPGM
Min
VSS-0.3 4
Max
17.5 10
Unit
V ms years
AGREEMENT
16.10 Power Driver Characteristics
(All voltages are referenced to VSS, VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, inductive load at the Power Drivers Outputs (PE7-0,PF3-0): L=100 mH, R=260)
Characteristic Operating Supply Voltage for Power Drivers(1) Output High Voltage IOH = -35 mA PE7-0, PF3-0 Output Low Voltage IOL = +35 mA PE7-0, PF3-0 Output Rise Time (2) 10% to 90% of VOH, PVDD = 8V, T = +25C PE7-0, PF3-0 Output Fall Time (note 2) 90% to 10% of VOH, PVDD = 8V, T = +25C PE7-0, PF3-0
Symbol PVDD VOH
Min VDD PVDD - 0.5
Typ -- --
Max 9.5 PVDD + 0.5
Unit V V
NON-DISCLOSURE
VOL
0
--
0.5
V
tr
21
--
--
ns
tf
19
--
--
ns
1. The value for the supply voltage for the power driver is under normal operating conditions as well as under short circuit conditions. 2. The power driver outputs are slew rate limited. The value show the minimal time for an inductive load (L=100 mH, R=260) which is connected to PVDD.
General Release Specification 180 Electrical Characteristics
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Electrical Characteristics Power-on Reset/Low Voltage Reset Characteristics
16.11 Power-on Reset/Low Voltage Reset Characteristics
(VDD = 5.0Vdc10%, VSS = 0Vdc, TA = -40C to +85C, unless otherwise noted)
Characteristic Low Voltage Reset (LVR) - Threshold Voltage VRON - (VDD Increasing) VROFF - (VDD Decreasing) Hysteresis Minimum Reset Voltage Supply Voltage Rise and Fall Time Low Voltage Reset Internal Delay Time
Symbol
Min
Typ (1)
Max
Unit
VRON VROFF VHYST Vmin -- --
3.4 3.3 0.1 1.0 -- --
3.85 3.75 -- -- -- 5
4.3 4.2 -- -- 1000 --
V V V V
ms
1. Typical values reflect average measurements at midpoint of voltage range at 25 C.
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Electrical Characteristics
General Release Specification 181
NON-DISCLOSURE
AGREEMENT
ms
REQUIRED
Electrical Characteristics REQUIRED NON-DISCLOSURE
General Release Specification 182 Electrical Characteristics
AGREEMENT
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Section 17. Mechanical Specifications
17.1 Contents
17.2 17.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
17.2 Pin Assignments
7 VREFH AVDD VDD PC0/TCAP0 PC1/TCAP1 PC2/TCAP2 PC3/TCAP3 PC4/TCMP0 PC5/TCMP1 PC6/RDI PC7/TDO PVDD2 PVSS2 20 21 PE7 PE6 PE5 PE4 PF3 PF2 27 PF1 PF0 PE3 PE2 PE1 PE0 14 8 1
47 46 PB3 PB2/ECLK PB1 PB0 PA7 PA6 40 PA5 PA4 PA3 PA2 PA1 PA0 34 33 PVSS1 PVDD1
Figure 17-1. 52-Pin PLCC Pin Assignments
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA Mechanical Specifications
General Release Specification 183
NON-DISCLOSURE
AGREEMENT
PB6/MOSI
PB5/MISO
PB7/SCK
PD3/AN3
PD2/AN2
PD1/AN1
PD0/AN0
IRQ/VPP
RESET
OSC1
OSC2
VSS
PB4
REQUIRED
Mechanical Specifications REQUIRED 17.3 Package Dimensions
0.18 M T N S -P S
L
S -M S
B
-N-
Y BRK
AGREEMENT
-L-
Case No. 778-02 52 Lead PLCC
W
-M-
G1
Z1
pin 52
-P-
pin 1 V
X U 0.18 M T N S -P S 0.18 M T L S -M S 0.18 M T L S -M S L
S -M S
A R Z C
N S -P S N S -P S
0.10
NON-DISCLOSURE
G G1 0.25 S T L S -M S
JE N S -P S
-T- SEATING PLANE
Dim. A B C E F G H J K R
Min. Max. 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 19.05 19.20
Notes
1. Datums -L-, -M-, -N- and -P- are determined where top of lead shoulder exits plastic body at mould parting line. 2. Dimension G1, true position to be measured at datum -T- (seating plane). 3. Dimensions R and U do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. 4. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 5. All dimensions in mm.
Dim. U V W X Y Z G1 K1 Z1
Min. 19.05 1.07 1.07 1.07 -- 2 18.04 1.02 2
Max. 19.20 1.21 1.21 1.42 0.50 10 18.54 -- 10
Figure 17-2. 52-Pin PLCC Package Dimensions
General Release Specification 184 Mechanical Specifications
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
General Release Specification -- MC68HC(7)05H12
Index
16-bit timer block diagram 104 interrupts 64 register addresses 105 52-pin PLCC case outline 184 52-pin PLCC package 20, 183 8-bit timer see core timer
B
bit manipulation instructions 50 block diagrams 16-bit timer 104 core timer 98 MC68HC(7)05H12 19 PWM 160 SCI 128 SPI 119 bootloader 167
A
A/D channel assignments 147 clock selection 147 conversion accuracy 150 data register (ADDR) 148 electrical characteristics 178 errors 151 status and control register (ADSCR) 146, 147 accumulator 39 address mark wake-up 131 addressing modes 42 ADON bit in ADSCR 146 ADRC bit in ADSCR 146 ALU -- arithmetic/logic unit 42 AN0-AN3 23 analog input 148 analog to digital converter see A/D AVDD 21
C
carry/borrow flag 41 C-bit in CCR 41 CH3_0 bits in ADSCR 147 channel microshifting 161 CO2E bit in TCR2 112 COCO bit in ADSCR 146 COIE bit in TCR1 111 condition code register (CCR) 40 control instructions 51 control timing 178 COP register (COPR) 72 reset 70, 101 COPE bit in MOR 171 COPR bit in COPR 72 core timer block diagram 98 counter register (CTCR) 101 interrupts 64
General Release Specification 185
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
Index
status and control register (CTSCR) 99 counter 105 CPHA bit in SPCR 122 CPOL bit in SPCR 122 cross coupled coils 85 extended addressing mode 43 external interrupt 63
F
FE bit in SCSR 139 features 18 flowcharts interrupt 62 WAIT 77
D
data retention mode 78 DC electrical characteristics 176 differential linearity error 151 direct addressing mode 43 DOD bit in SPCR 121
G
gain scale error 151
E
ECLK bit in SYSCR 34 ECLK pin 22 EDGE7-0 bits in PAIED 81 EELAT bit in EEPCR 155 EEOSC bit in EEPCR 154 EEPGM bit in EEPCR 155 EEPROM 35 control register (EEPCR) 154, 155 electrical characteristics 179 erase 156 options register (EEOPR) 155, 156 programming 157 read 156 EEPRT bit in EEOPR 156 EER1, EER0 bits in EEPCR 154 ELAT bit in EPROG 170 EPGM bit in EPROG 170 EPROM 35 bootloader 167 electrical characteristics 180 programming 170 programming register (EPROG) 170 erase mode select 154
H
half-carry flag 41 hardware interrupts 63-65 H-bit in CCR 41 H-bridge driver 86 states 90 with the PWM 94
I
I/O programming 95 IC1F bit in TSR 113 IC2F bit in TSR 113 ICI1E bit in TCR1 111 ICI2E bit in TCR1 111 IDLE bit in SCSR 139 idle line wake-up 131 IEDG1 bit in TCR1 111 IEDG2 bit in TCR1 111 ILIE bit in SCCR2 137 illegal address reset 72 immediate addressing mode 43 index register 39 indexed addressing mode 44
General Release Specification 186
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
Index
inherent addressing mode 43 input capture register 1 108 register 2 109 instruction types 45 integral linearity error 151 interrupts 16-bit timers 64 core timer 64 flowchart 62 hardware 63 IRQ 63 keyboard 63 SCI 65 SPI 65 SWI 63 IRQ bit in SYSCR 34 IRQ pin 21
maximum ratings 174 memory map 26 MISO 22, 116 modes of operation data retention 78 entry conditions 75 low power (WAIT) 65, 76-78 monitor 76 slow 78 user 75 monitor mode 76 monitor ROM 35 monotonicity 150 MOR 171 MOSI 22, 117 MSTR bit in SPCR 121
N
N-bit in CCR 41 negative flag 41 NF bit in SCSR 139
J
jump/branch instructions 48 junction temperature, chip 175
O K
keyboard interrupt 22, 63, 80 OC1F bit in TSR 113 OC2F bit in TSR 114 OCI1E bit in TCR1 111 OCI2E bit in TCR2 112 offset error 151 OLVL1 bit in TCR1 111 OLVL2 bit in TCR2 112 opcode map 58 operating modes see modes of operation OR bit in SCSR 139 OSC1, OSC2 21 oscillator pins 21 output compare 106
L
low power modes 65, 76 low voltage reset (LVR) 72 electrical characteristics 181
M
M bit in SCCR1 136 mask options 20 register (MOR) 171 master mode 120
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
General Release Specification 187
Index
register 1 106 register 2 107 port A interrupt control register (PAICR) 81 interrupt edge register (PAIED) 81 interrupt status register (PAISR) 82 keyboard interrupt 80 port B 82 port C 83 port D 83 port E and port F configurations 92 mismatch registers (PEMISM and PFMISM)
89, 90
P
PA0-PA7 22 PAIE7-0 bits in PAICR 81 PAIF7-0 bits in PAISR 82 PB0-PB7 22 PC0-PC7 22 PD0-PD3 23 PE0-PE7 23 PF0-PF3 23 pins AN0-AN3 23 assignments 20 AVDD 21 ECLK 22 IRQ 21 keyboard interrupt 22 MISO 22 MOSI 22 OSC1, OSC2 21 port A (PA0-PA7) 22 port B (PB0-PB7) 22 port C (PC0-PC7) 22 port D (PD0-PD3) 23 port E (PE0-PE7) 23 port F (PF0-PF3) 23 PVDD1, PVSS1, PVDD2, PVSS2 23 RDI 22 RESET 21 SCK 22 TCAP0-3 22 TCMP0-1 22 TDO 22 VDD, VSS 21 VPP 21 VREFH 23
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
power drivers 83 power considerations 175 power driver circuit 87 electrical characteristics 180 pins 23, 83 power supply pins 21 power-on reset (POR) 70 electrical characteristics 181 PPOL7-0 bits in PWMPOL 165 program counter 40 programming circuit 169 programming model 38 pulse width modulator see PWM PVDD1, PVSS1, PVDD2, PVSS2 23 PWDRW bit in MOR 171 PWM block diagram 160 channel enable register (PWMEN) 165 channel microshifting 161 channel polarity register (PWMPOL) 165 control register (PWMCTL) 164 data registers (PWM0-7) 163 PWMC3-1 bits in PWMCTL 164 PWME7-0 bits in PWMEN 165
General Release Specification 188
Index
Index
PWMRST bit in PWMCTL 164
Q
quantization error 151
R
R8 bit in SCCRI 136 RAM 35 RCKB bit in BAUD 141 RDI 22 RDRF bit in SCSR 139 RE bit in SCCR2 138 read-modify-write instructions 47 receive data (RDI) 132 receiver 130 register/memory instructions 46 registers ADDR 148 ADSCR 146 BAUD 140 complete listing 29-33 COPR 72 CTCR 102 CTSCR 99 EEOPR 155 EEPCR 154 EPROG 170 MOR 171 PAICR 81 PAIED 81 PAISR 82 PEMISM 89 PFMISM 90 PWM07 163 PWMCTL 164 PWMEN 165 PWMPOL 165
SCCR1 136 SCCR2 137 SCDAT 135 SCSR 138 SPCR 121 SPDAT 124 SPSR 123 summary 27 SYSCR 34 TCR1 110 TCR2 112 TSR 113 relative addressing mode 45 RESET 21, 67 resets computer operating properly (COPR) 70 external 67 illegal address 72 internal 68 LVR 72 POR 70 RESET 67 RIE bit in SCCR2 137 ROM 35 RRTIF bit in CTSCR 100 RT1, RT0 bits in CTSCR 100 RTI rates 100 RTIE bit in CTSCR 100 RTIF bit in CTSCR 99 RTOF bit in CTSCR 100 RWU bit in SCCR2 138
S
SBK bit in SCCR2 138 SC bit in SYSCR 34 SCI baud rate register (BAUD) 140, 141 block diagram 128
General Release Specification 189
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
Index
control register 1 (SCCR1) 136 control register 2 (SCCR2) 137, 138 data format 130 data register (SCDAT) 135 interrupt 65 receiver wake-up 130 status register (SCSR) 138, 139 SCK 22, 117 SCP1, SCPO bits in BAUD 141 SCR2, SCR1, SCRO bits in BAUD 141 serial communcations interface see SCI serial peripheral interface see SPI short circuit detection 88 SIGN3-0 bits in PWMCTL 164 slave mode 120 slow mode 78 software interrupt (SWI) 63 SPE bit in SPCR 121 SPI block diagram 119 control register (SPCR) 121, 122 data I/O register (SPDAT) 124 interrupt 65 master and slave 120 MISO 116 MOSI 117 serial clock (SCK) 117 status register (SPSR) 123 SPIE bit in SPCR 121 SPIF bit in SPSR 123 SPP bit in BAUD 140 SPR1, SPR0 bits in SPCR 122 stack pointer 39 start bit 132 system control register (SYSCR) 34 ECLK -- internal system clock available 34
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
IRQ -- IRQ sensitivity 34 SC -- system clock option 34
T
T8 bit in SCCR1 136 TC bit in SCSR 139 TCAP0-3 22 TCAP1 bit in TSR 113 TCAP2 bit in TSR 113 TCIE bit in SCCR2 137 TCLR bit in BAUD 140 TCMP0-1 22 TDO 22 TDRE bit in SCSR 139 TE bit in SCCR2 137 thermal characteristics 175 TIE bit in SCCR2 137 timer control register 1 (TCR1) 110 CO1E -- timer compare 1 output enable 111 ICI1E -- input capture 1 interrupt enable 111 ICI2E -- input capture 2 interrupt enable 111 IEDG1 -- input edge 111 IEDG2 -- input edge 111 OCI1E -- output compare 1 interrupt enable
111
OLVL1 -- output level 1 111 TOIE -- timer overflow interrupt enable 111 timer control register 2 (TCR2) 112 CO2E -- timer compare 2 output enable 112 OCI2E -- output compare 2 interrupt enable
112
OLVL2 -- output level 2 112 timer status register (TSR) 113 IC1F -- input capture 1 flag 113 IC1F -- output compare 1 flag 113 IC2F -- input capture 2 flag 113 IC2F -- output compare 2 flag 114 TCAP1 -- timer capture 1 113
General Release Specification 190
Index
Index
TCAP2 -- timer capture 2 113 TOF -- timer overflow flag 113 timing diagrams data clock 118 RESET and POR 69 TOF bit in CTSCR 99 TOF bit in TSR 113 TOFE bit in CTSCR 100 TOIE bit in TCR1 111 total unadjusted error 151 transfer curve 150 transmit data (TDO) 135
U
user mode 75
V
VDD, VSS 21 vector addresses 61 VPP 21 VREFH 23
W
WAIT mode 65, 77 WAKE bit in SCCR1 136 wake-up 130 address mark 131 idle line 131 watchdog see COP WCOL bit in SPSR 123
Z
Z-bit in CCR 41 zero flag 41
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
General Release Specification 191
Index
MC68HC(7)05H12 -- Rev. 1.0 MOTOROLA
Index
General Release Specification 192
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217.1-800-441-2447 or 303-675-2140 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://www.mot.com/SPS/ JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
Mfax is a trademark of Motorola, Inc. (c) Motorola, Inc., 1997
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